Message-ID: <20240627173251.25718-2-fancer.lancer@gmail.com>
Date: Thu, 27 Jun 2024 20:32:08 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Michal Simek <michal.simek@....com>,
	Alexander Stein <alexander.stein@...tq-group.com>,
	Borislav Petkov <bp@...en8.de>,
	Tony Luck <tony.luck@...el.com>,
	James Morse <james.morse@....com>,
	Mauro Carvalho Chehab <mchehab@...nel.org>,
	Robert Richter <rric@...nel.org>,
	Manish Narani <manish.narani@...inx.com>
Cc: Serge Semin <fancer.lancer@...il.com>,
	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>,
	Dinh Nguyen <dinguyen@...nel.org>,
	Shubhrajyoti Datta <shubhrajyoti.datta@...il.com>,
	Arnd Bergmann <arnd@...db.de>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	linux-arm-kernel@...ts.infradead.org,
	linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Shubhrajyoti Datta <shubhrajyoti.datta@....com>,
	Borislav Petkov <bp@...e.de>
Subject: [PATCH RESEND v6 01/18] EDAC/synopsys: Fix generic device type detection procedure

First of all the enum dev_type constants describe the memory DRAM chips
used at the stick, not the entire DQ-bus width (see the enumeration kdoc
for details). So what is returned from the zynqmp_get_dtype() function and
then specified to the dimm_info->dtype field is definitely incorrect
because the DDR controller DQ-bus width doesn't determine a strict
DDR-chips configuration on the attached memory device.

Secondly the DRAM chips type has nothing to do with the data bus width
specified in the MSTR.data_bus_width CSR field. The CSR field just
determines the _part_ of the whole DQ-bus currently used to access the data
from the all DRAM memory chips. So it doesn't indicate the individual
chips type.

Thirdly in case of the DW uMCTL2 controllers the DRAM chips type can be
firmly determined only in case of the DDR4 protocol by means of the
MSTR.device_config field state (the field is supposed to be set by the system
firmware though). From this and the rest of the perspective the
zynqmp_get_dtype() implementation is incorrect.

Finally the DW uMCTL2 DDRC ECC capability doesn't depend on the memory
chips type. Moreover it doesn't depend on the utilized data bus width in
runtime either. The IP-core reference manual says in [1,2] that the ECC
support can't be enabled during the IP-core synthesis for the DRAM data
bus widths other than 16, 32 or 64. At the same time the bus width mode
(MSTR.data_bus_width) doesn't change the ECC feature availability. Thus it
was wrong to determine the ECC state with respect to the DQ-bus width
mode. From this perspective the zynqmp_get_ecc_state() implementation is
incorrect either. It shouldn't rely on the currently utilized DQ-bus
part or the attached DDR-chip types.

Fix all of the mistakes described above in the zynqmp_get_dtype() and
zynqmp_get_ecc_state() methods: determine the actual DRAM chips data width
only for the DDR4 protocol and return that it's UNKNOWN in the rest of the
cases; determine the ECC availability by the ECCCFG0.ecc_mode field state
only (that field can't be modified anyway if the IP-core was synthesized
with no ECC support).

[1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2)
Databook, Version 3.91a, October 2020, p. 421.
[2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2)
Databook, Version 3.91a, October 2020, p. 633.

Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller")
Signed-off-by: Serge Semin <fancer.lancer@...il.com>
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>

---

Changelog v2:
- Include "linux/bitfield.h" header file to get the FIELD_GET macro
  definition. (@tbot)

Changelog v6:
- Fix the zynqmp_get_dtype() method kdoc.
- Split up the commit log into paragraphs.
---
 drivers/edac/synopsys_edac.c | 55 +++++++++++++++---------------------
 1 file changed, 23 insertions(+), 32 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index ea7a9a342dd3..b6bdbc1289f3 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -664,36 +664,35 @@ static enum dev_type zynq_get_dtype(const void __iomem *base)
 }
 
 /**
- * zynqmp_get_dtype - Return the controller memory width.
+ * zynqmp_get_dtype - Return the DDR memory chips type.
  * @base:	DDR memory controller base address.
  *
- * Get the EDAC device type width appropriate for the current controller
+ * Get the attached DDR chips type based on the current controller
  * configuration.
  *
- * Return: a device type width enumeration.
+ * Return: type of the memory DRAM chips.
  */
 static enum dev_type zynqmp_get_dtype(const void __iomem *base)
 {
-	enum dev_type dt;
-	u32 width;
-
-	width = readl(base + CTRL_OFST);
-	width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
-	switch (width) {
-	case DDRCTL_EWDTH_16:
-		dt = DEV_X2;
-		break;
-	case DDRCTL_EWDTH_32:
-		dt = DEV_X4;
-		break;
-	case DDRCTL_EWDTH_64:
-		dt = DEV_X8;
-		break;
-	default:
-		dt = DEV_UNKNOWN;
+	u32 regval;
+
+	regval = readl(base + CTRL_OFST);
+	if (!(regval & MEM_TYPE_DDR4))
+		return DEV_UNKNOWN;
+
+	regval = (regval & DDRC_MSTR_CFG_MASK) >> DDRC_MSTR_CFG_SHIFT;
+	switch (regval) {
+	case DDRC_MSTR_CFG_X4_MASK:
+		return DEV_X4;
+	case DDRC_MSTR_CFG_X8_MASK:
+		return DEV_X8;
+	case DDRC_MSTR_CFG_X16_MASK:
+		return DEV_X16;
+	case DDRC_MSTR_CFG_X32_MASK:
+		return DEV_X32;
 	}
 
-	return dt;
+	return DEV_UNKNOWN;
 }
 
 /**
@@ -730,19 +729,11 @@ static bool zynq_get_ecc_state(void __iomem *base)
  */
 static bool zynqmp_get_ecc_state(void __iomem *base)
 {
-	enum dev_type dt;
-	u32 ecctype;
+	u32 regval;
 
-	dt = zynqmp_get_dtype(base);
-	if (dt == DEV_UNKNOWN)
-		return false;
+	regval = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
 
-	ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
-	if ((ecctype == SCRUB_MODE_SECDED) &&
-	    ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
-		return true;
-
-	return false;
+	return (regval == SCRUB_MODE_SECDED);
 }
 
 /**
-- 
2.43.0

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