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Message-ID: <20240627152708.3abda399@jacob-builder>
Date: Thu, 27 Jun 2024 15:27:08 -0700
From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
To: Sohil Mehta <sohil.mehta@...el.com>
Cc: x86@...nel.org, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar
<mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Dave Hansen
<dave.hansen@...ux.intel.com>, "H . Peter Anvin" <hpa@...or.com>,
linux-kernel@...r.kernel.org, jacob.jun.pan@...ux.intel.com
Subject: Re: [PATCH v2] x86/irq: Fix comment on IRQ vector layout
On Wed, 26 Jun 2024 19:43:24 +0000, Sohil Mehta <sohil.mehta@...el.com>
wrote:
> commit f5a3562ec9dd ("x86/irq: Reserve a per CPU IDT vector for posted
> MSIs") changed the first system vector from LOCAL_TIMER_VECTOR to
> POSTED_MSI_NOTIFICATION_VECTOR. Reflect this change in the vector layout
> comment as well.
>
> However, instead of pointing to the specific vector, use the
> FIRST_SYSTEM_VECTOR indirection which essentially refers to the same.
> This would avoid unnecessary modifications to the same comment whenever
> additional system vectors get added.
>
> Signed-off-by: Sohil Mehta <sohil.mehta@...el.com>
> ---
> v2: Update the table to denote the other device interrupts range. [Jacob
> Pan]
>
> v1:
> https://lore.kernel.org/lkml/20240618201320.2066726-1-sohil.mehta@intel.com/
>
> arch/x86/include/asm/irq_vectors.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/irq_vectors.h
> b/arch/x86/include/asm/irq_vectors.h index 13aea8fc3d45..47051871b436
> 100644 --- a/arch/x86/include/asm/irq_vectors.h
> +++ b/arch/x86/include/asm/irq_vectors.h
> @@ -18,8 +18,8 @@
> * Vectors 0 ... 31 : system traps and exceptions - hardcoded events
> * Vectors 32 ... 127 : device interrupts
> * Vector 128 : legacy int80 syscall interface
> - * Vectors 129 ... LOCAL_TIMER_VECTOR-1
> - * Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts
> + * Vectors 129 ... FIRST_SYSTEM_VECTOR-1 : device interrupts
> + * Vectors FIRST_SYSTEM_VECTOR ... 255 : special interrupts
> *
> * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
> *
Reviewed-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
Thanks,
Jacob
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