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Message-ID: <1e32a8b4-0cae-47c7-9112-f0b6e78bf31b@collabora.com>
Date: Thu, 27 Jun 2024 10:39:01 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Yassine Oudjana <yassine.oudjana@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>, Daniel Golle
<daniel@...rotopia.org>, jason-ch chen <Jason-ch.Chen@...iatek.com>,
Sam Shih <sam.shih@...iatek.com>, Bartosz Golaszewski <brgl@...ev.pl>
Cc: Yassine Oudjana <y.oudjana@...tonmail.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 2/2] clk: mediatek: Add drivers for MediaTek MT6735
main clock and reset drivers
Il 26/06/24 22:24, Yassine Oudjana ha scritto:
> From: Yassine Oudjana <y.oudjana@...tonmail.com>
>
> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
> clock and reset controllers. These provide the base clocks and resets
> on the platform, enough to bring up all essential blocks including
> PWRAP, MSDC and peripherals (UART, I2C, SPI).
>
> Signed-off-by: Yassine Oudjana <y.oudjana@...tonmail.com>
If the resets were properly bound, you'd get my R-b here. :-(
It's a 20 minutes job anyway, go-go-go! :) :) :)
Cheers,
Angelo
> ---
> MAINTAINERS | 4 +
> drivers/clk/mediatek/Kconfig | 9 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 138 +++++++
> drivers/clk/mediatek/clk-mt6735-infracfg.c | 79 ++++
> drivers/clk/mediatek/clk-mt6735-pericfg.c | 92 +++++
> drivers/clk/mediatek/clk-mt6735-topckgen.c | 394 +++++++++++++++++++
> 7 files changed, 717 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
> create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
> create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
> create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
>
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