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Message-ID: <6c9a791b-aaef-4ad0-a10d-ec3acb42ac32@linaro.org>
Date: Thu, 27 Jun 2024 13:55:57 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: xianwei.zhao@...ogic.com, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Jianxin Pan <jianxin.pan@...ogic.com>, Ulf Hansson <ulf.hansson@...aro.org>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, Hongyu Chen <hongyu.chen1@...ogic.com>
Subject: Re: [PATCH 2/3] pmdomain: amlogic: Add support for A5 power domains
controller
On 27/06/2024 13:47, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@...ogic.com>
>
> Add support for the A5 power controller, whose registers are
> in the secure domain and should be accessed via SMC.
>
> Signed-off-by: Hongyu Chen <hongyu.chen1@...ogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com>
> ---
> drivers/pmdomain/amlogic/meson-secure-pwrc.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c
> index df5567418226..f6729eea6b8c 100644
> --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c
> +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c
> @@ -15,6 +15,7 @@
> #include <dt-bindings/power/meson-s4-power.h>
> #include <dt-bindings/power/amlogic,t7-pwrc.h>
> #include <dt-bindings/power/amlogic,a4-pwrc.h>
> +#include <dt-bindings/power/amlogic,a5-pwrc.h>
> #include <linux/arm-smccc.h>
> #include <linux/firmware/meson/meson_sm.h>
> #include <linux/module.h>
> @@ -155,6 +156,22 @@ static struct meson_secure_pwrc_domain_desc a4_pwrc_domains[] = {
> SEC_PD(A4_AO_IR, GENPD_FLAG_ALWAYS_ON),
> };
>
> +static struct meson_secure_pwrc_domain_desc a5_pwrc_domains[] = {
> + SEC_PD(A5_NNA, 0),
> + SEC_PD(A5_AUDIO, 0),
> + SEC_PD(A5_SDIOA, 0),
> + SEC_PD(A5_EMMC, 0),
> + SEC_PD(A5_USB_COMB, 0),
> + SEC_PD(A5_ETH, 0),
> + SEC_PD(A5_RSA, 0),
> + SEC_PD(A5_AUDIO_PDM, 0),
> + /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
> + SEC_PD(A5_DMC, GENPD_FLAG_ALWAYS_ON),
> + /* WRAP is secure_top, a lot of modules are included, and should be always on */
> + SEC_PD(A5_SYS_WRAP, GENPD_FLAG_ALWAYS_ON),
> + SEC_PD(A5_DSPA, 0),
> +};
> +
> static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
> SEC_PD(C3_NNA, 0),
> SEC_PD(C3_AUDIO, 0),
> @@ -335,6 +352,11 @@ static struct meson_secure_pwrc_domain_data amlogic_secure_a4_pwrc_data = {
> .count = ARRAY_SIZE(a4_pwrc_domains),
> };
>
> +static struct meson_secure_pwrc_domain_data amlogic_secure_a5_pwrc_data = {
> + .domains = a5_pwrc_domains,
> + .count = ARRAY_SIZE(a5_pwrc_domains),
> +};
> +
> static struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = {
> .domains = c3_pwrc_domains,
> .count = ARRAY_SIZE(c3_pwrc_domains),
> @@ -359,6 +381,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = {
> .compatible = "amlogic,a4-pwrc",
> .data = &amlogic_secure_a4_pwrc_data,
> },
> + {
> + .compatible = "amlogic,a5-pwrc",
> + .data = &amlogic_secure_a5_pwrc_data,
> + },
> {
> .compatible = "amlogic,c3-pwrc",
> .data = &amlogic_secure_c3_pwrc_data,
>
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
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