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Message-ID: <f610effb-34af-4150-a320-c8882117b632@lunn.ch>
Date: Thu, 27 Jun 2024 17:15:54 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Vladimir Oltean <olteanv@...il.com>,
	Woojung Huh <woojung.huh@...rochip.com>,
	Arun Ramadoss <arun.ramadoss@...rochip.com>,
	Lucas Stach <l.stach@...gutronix.de>, kernel@...gutronix.de,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
	UNGLinuxDriver@...rochip.com
Subject: Re: [PATCH net-next v1 2/3] net: dsa: microchip: lan937x: force
 RGMII interface into PHY mode

On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote:
> From: Lucas Stach <l.stach@...gutronix.de>
> 
> The register manual and datasheet documentation for the LAN937x series
> disagree about the polarity of the MII mode strap. As a consequence
> there are hardware designs that have the RGMII interface strapped into
> MAC mode, which is a invalid configuration and will prevent the internal
> clock from being fed into the port TX interface.

What i think is missing from this is that you are talking about the
CPU port. For a normal user point, RGMII MAC mode would make sense, if
there is an external RGMII PHY attached. And the code only does this
if the port is a CPU port.

So maybe:

... that have the CPU port RGMII interface ...

	Andrew

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