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Message-ID: <Zn8rSzCVoVBYTf8R@Asurada-Nvidia>
Date: Fri, 28 Jun 2024 14:29:47 -0700
From: Nicolin Chen <nicolinc@...dia.com>
To: Pavel Machek <pavel@....cz>
CC: <will@...nel.org>, <robin.murphy@....com>, <joro@...tes.org>,
	<jgg@...dia.com>, <thierry.reding@...il.com>, <vdumpa@...dia.com>,
	<jonathanh@...dia.com>, <linux-kernel@...r.kernel.org>,
	<iommu@...ts.linux.dev>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-tegra@...r.kernel.org>
Subject: Re: [PATCH v9 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2)

On Fri, Jun 28, 2024 at 09:26:00PM +0200, Pavel Machek wrote:
> Hi!
> 
> > NVIDIA's Tegra241 (Grace) SoC has a CMDQ-Virtualization (CMDQV) hardware
> > that extends standard ARM SMMUv3 to support multiple command queues with
> > virtualization capabilities. Though this is similar to the ECMDQ in SMMU
> > v3.3, CMDQV provides additional Virtual Interfaces (VINTFs) allowing VMs
> > to have their own VINTFs and Virtual Command Queues (VCMDQs). The VCMDQs
> > can only execute a limited set of commands, mainly invalidation commands
> > when exclusively used by the VMs, compared to the standard SMMUv3 CMDQ.
> 
> Text is block-aligned without duplicated spaces. How did you do
> that...?

By OCD? Nothing fancy :)

Thanks
Nicolin

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