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Message-ID: <79e57338-1671-4574-b1e2-3b3aa9045ec9@gmail.com>
Date: Thu, 27 Jun 2024 23:39:10 -0500
From: "Alex G." <mr.nuke.me@...il.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, linux-kernel@...r.kernel.org,
quic_kathirav@...cinc.com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v4 8/8] arm64: dts: qcom: ipq9574: add PCIe2 and PCIe3
nodes
On 6/23/24 23:18, Manivannan Sadhasivam wrote:
> On Tue, Apr 30, 2024 at 11:07:50PM -0500, Alexandru Gagniuc wrote:
>> On ipq9574, there are 4 PCIe controllers. Describe the pcie2 and pcie3
>> nodes, and their PHYs in devicetree.
>>
>> The pcie0 and pcie1 controllers use a gen3x1 PHY, which is not
>> currently supported. Hence, only pcie2 and pcie3 are described. Only
>> pcie2 was tested because my devboard only has conenctions to pcie2.
>>
>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@...il.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 178 +++++++++++++++++++++++++-
>> 1 file changed, 176 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 7f2e5cbf3bbb..c391886cf9ab 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -300,8 +300,8 @@ gcc: clock-controller@...0000 {
>> <0>,
>> <0>,
>> <0>,
>> - <0>,
>> - <0>,
>> + <&pcie2_phy>,
>> + <&pcie3_phy>,
>> <0>;
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> @@ -745,6 +745,180 @@ frame@...8000 {
>> status = "disabled";
>> };
>> };
>> +
>> + pcie2_phy: phy@...00 {
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x0008c000 0x14f4>;
>> +
>> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
>> + <&gcc GCC_PCIE2_AHB_CLK>,
>> + <&gcc GCC_PCIE2_PIPE_CLK>;
>> + clock-names = "aux",
>> + "cfg_ahb",
>> + "pipe";
>> +
>> + clock-output-names = "pcie_phy2_pipe_clk";
>> + #clock-cells = <0>;
>> + #phy-cells = <0>;
>> +
>> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
>> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
>> + reset-names = "phy",
>> + "common";
>> + status = "disabled";
>> + };
>> +
>> + pcie3_phy: phy@...00 {
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x000f4000 0x14f4>;
>> +
>> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
>> + <&gcc GCC_PCIE3_AHB_CLK>,
>> + <&gcc GCC_PCIE3_PIPE_CLK>;
>> + clock-names = "aux",
>> + "cfg_ahb",
>> + "pipe";
>> +
>> + clock-output-names = "pcie_phy3_pipe_clk";
>> + #clock-cells = <0>;
>> + #phy-cells = <0>;
>> +
>> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
>> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
>> + reset-names = "phy",
>> + "common";
>> + status = "disabled";
>> + };
>> +
>> + /* TODO: Populate pcie0/pcie1 when gen3x1 phy support is added. */
>> +
>> + pcie2: pcie@...00000 {
>> + compatible = "qcom,pcie-ipq9574";
>> + reg = <0x20000000 0xf1d>,
>> + <0x20000f20 0xa8>,
>> + <0x20001000 0x1000>,
>> + <0x00088000 0x4000>,
>> + <0x20100000 0x1000>;
>> + reg-names = "dbi", "elbi", "atu", "parf", "config";
>> +
>> + ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>,
>> + <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>;
>
> Please cross check 'ranges' property with other platforms.
>
<snip>
>
> Cross check 'interrupt-map' as well.
I'm not seeing the smoking gun. What am I looking for?
Alex
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