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Message-ID: <202406281241.xEX0TWjt-lkp@intel.com>
Date: Fri, 28 Jun 2024 13:18:18 +0800
From: kernel test robot <lkp@...el.com>
To: Bibek Kumar Patro <quic_bibekkum@...cinc.com>, robdclark@...il.com,
will@...nel.org, robin.murphy@....com, joro@...tes.org,
jgg@...pe.ca, jsnitsel@...hat.com, robh@...nel.org,
krzysztof.kozlowski@...aro.org, quic_c_gdjako@...cinc.com,
dmitry.baryshkov@...aro.org, konrad.dybcio@...aro.org
Cc: oe-kbuild-all@...ts.linux.dev, iommu@...ts.linux.dev,
linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Bibek Kumar Patro <quic_bibekkum@...cinc.com>
Subject: Re: [PATCH v12 6/6] iommu/arm-smmu: add support for PRR bit setup
Hi Bibek,
kernel test robot noticed the following build warnings:
[auto build test WARNING on joro-iommu/next]
[also build test WARNING on linus/master v6.10-rc5 next-20240627]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Bibek-Kumar-Patro/iommu-arm-smmu-re-enable-context-caching-in-smmu-reset-operation/20240627-074037
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
patch link: https://lore.kernel.org/r/20240626143020.3682243-7-quic_bibekkum%40quicinc.com
patch subject: [PATCH v12 6/6] iommu/arm-smmu: add support for PRR bit setup
config: arm64-randconfig-r113-20240628 (https://download.01.org/0day-ci/archive/20240628/202406281241.xEX0TWjt-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240628/202406281241.xEX0TWjt-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406281241.xEX0TWjt-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: expected void volatile [noderef] __iomem *addr
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:247:54: sparse: got void *
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: expected void volatile [noderef] __iomem *addr
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:250:54: sparse: got void *
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/slab.h, ...):
include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false
include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false
vim +247 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
238
239 static void qcom_adreno_smmu_set_prr(const void *cookie, phys_addr_t page_addr, bool set)
240 {
241 struct arm_smmu_domain *smmu_domain = (void *)cookie;
242 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
243 struct arm_smmu_device *smmu = smmu_domain->smmu;
244 u32 reg = 0;
245
246 writel_relaxed(lower_32_bits(page_addr),
> 247 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
248
249 writel_relaxed(upper_32_bits(page_addr),
250 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
251
252 reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
253 reg &= ~GFX_ACTLR_PRR;
254 if (set)
255 reg |= FIELD_PREP(GFX_ACTLR_PRR, 1);
256 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
257
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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