linux-kernel - Re: [RFC PATCH] drm/msm/dpu: check ubwc support before adding compressed formats

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Message-ID: <19c49c3b-057c-ce83-1ec6-4929676ff0e7@quicinc.com>
Date: Thu, 27 Jun 2024 22:43:57 -0700
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Rob Clark <robdclark@...il.com>, <freedreno@...ts.freedesktop.org>,
        "Sean
 Paul" <sean@...rly.run>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        "David Airlie" <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
        <dri-devel@...ts.freedesktop.org>, <quic_jesszhan@...cinc.com>,
        <konrad.dybcio@...aro.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH] drm/msm/dpu: check ubwc support before adding
 compressed formats



On 6/27/2024 4:22 PM, Dmitry Baryshkov wrote:
> On Fri, 28 Jun 2024 at 00:21, Abhinav Kumar <quic_abhinavk@...cinc.com> wrote:
>>
>>
>>
>> On 6/27/2024 2:13 PM, Rob Clark wrote:
>>> On Thu, Jun 27, 2024 at 1:53 PM Abhinav Kumar <quic_abhinavk@...cinc.com> wrote:
>>>>
>>>> On QCM2290 chipset DPU does not support UBWC.
>>>>
>>>> Add a dpu cap to indicate this and do not expose compressed formats
>>>> in this case.
>>>>
>>>> Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
>>>> ---
>>>>    drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 +
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h          | 2 ++
>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c               | 5 ++++-
>>>>    3 files changed, 7 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
>>>> index 3cbb2fe8aba2..6671f798bacc 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
>>>> @@ -12,6 +12,7 @@ static const struct dpu_caps qcm2290_dpu_caps = {
>>>>           .max_mixer_blendstages = 0x4,
>>>>           .has_dim_layer = true,
>>>>           .has_idle_pc = true,
>>>> +       .has_no_ubwc = true,
>>>>           .max_linewidth = 2160,
>>>>           .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>    };
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>> index af2ead1c4886..676d0a283922 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>> @@ -342,6 +342,7 @@ struct dpu_rotation_cfg {
>>>>     * @has_dim_layer      dim layer feature status
>>>>     * @has_idle_pc        indicate if idle power collapse feature is supported
>>>>     * @has_3d_merge       indicate if 3D merge is supported
>>>> + * @has_no_ubwc        indicate if UBWC is supported
>>>>     * @max_linewidth      max linewidth for sspp
>>>>     * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>>>>     * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
>>>> @@ -354,6 +355,7 @@ struct dpu_caps {
>>>>           bool has_dim_layer;
>>>>           bool has_idle_pc;
>>>>           bool has_3d_merge;
>>>> +       bool has_no_ubwc;
>>>
>>> has_no_ubwc sounds kinda awkward compared to has_ubwc.  But I guess
>>> you wanted to avoid all that churn..
>>>
>>
>> Yes I wanted to avoid modifying all the catalogs.
>>
>>> How about instead, if msm_mdss_data::ubwc_{enc,dec}_version are zero,
>>> then we know there is no ubwc support in the display.
>>>
>>
>> hmm ... should work .... I can post a v2 with this and avoid touching
>> the catalog altogether.
> 
> Yes, this sounds much better.
> 

Ok, does this qualify for a Fixes tag too? Because exposing ubwc formats 
on non-ubwc supported chipsets seems like a bug.