linux-kernel - Re: [PATCH V3 01/13] perf/x86/intel: Support the PEBS event mask

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Date: Fri, 28 Jun 2024 10:42:48 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: kan.liang@...ux.intel.com
Cc: mingo@...nel.org, acme@...nel.org, namhyung@...nel.org,
	irogers@...gle.com, adrian.hunter@...el.com,
	alexander.shishkin@...ux.intel.com, linux-kernel@...r.kernel.org,
	ak@...ux.intel.com, eranian@...gle.com
Subject: Re: [PATCH V3 01/13] perf/x86/intel: Support the PEBS event mask

On Wed, Jun 26, 2024 at 07:35:33AM -0700, kan.liang@...ux.intel.com wrote:

> @@ -1661,6 +1661,16 @@ static inline int is_ht_workaround_enabled(void)
>  	return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
>  }
>  
> +static inline u64 intel_pmu_pebs_mask(u64 cntr_mask)
> +{
> +	return MAX_PEBS_EVENTS_MASK & cntr_mask;
> +}
> +
> +static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
> +{
> +	return find_last_bit((unsigned long *)&hybrid(pmu, pebs_events_mask), MAX_PEBS_EVENTS) + 1;

I'll write that like:

	static_assert(MAX_PEBS_EVENTS == 32);
	return fls((u32)hybrid(pmu, pebs_events_mask));

> +}
> +
>  #else /* CONFIG_CPU_SUP_INTEL */
>  
>  static inline void reserve_ds_buffers(void)
> diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h
> index 2f9eeb5c3069..5dbeac48a5b9 100644
> --- a/arch/x86/include/asm/intel_ds.h
> +++ b/arch/x86/include/asm/intel_ds.h
> @@ -9,6 +9,7 @@
>  /* The maximal number of PEBS events: */
>  #define MAX_PEBS_EVENTS_FMT4	8
>  #define MAX_PEBS_EVENTS		32
> +#define MAX_PEBS_EVENTS_MASK	GENMASK_ULL(MAX_PEBS_EVENTS - 1, 0)
>  #define MAX_FIXED_PEBS_EVENTS	16
>  
>  /*
> -- 
> 2.38.1
>