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Message-Id: <20240628152348.61133-3-iansdannapel@gmail.com>
Date: Fri, 28 Jun 2024 17:23:47 +0200
From: iansdannapel@...il.com
To: Moritz Fischer <mdf@...nel.org>,
Wu Hao <hao.wu@...el.com>,
Xu Yilun <yilun.xu@...el.com>,
Tom Rix <trix@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko.stuebner@...rry.de>,
Neil Armstrong <neil.armstrong@...aro.org>,
Sebastian Reichel <sre@...nel.org>,
Chris Morgan <macromorgan@...mail.com>,
Michael Riesch <michael.riesch@...fvision.net>,
Rafał Miłecki <rafal@...ecki.pl>,
Andre Przywara <andre.przywara@....com>,
Linus Walleij <linus.walleij@...aro.org>,
linux-fpga@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Ian Dannapel <iansdannapel@...il.com>
Subject: [PATCH v2 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings
From: Ian Dannapel <iansdannapel@...il.com>
Add device tree binding documentation for configuring Efinix FPGA
using serial SPI passive programming mode.
Signed-off-by: Ian Dannapel <iansdannapel@...il.com>
---
.../fpga/efinix,trion-spi-passive.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
new file mode 100644
index 000000000000..d44a9d0627b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Efinix SPI FPGA Manager
+
+maintainers:
+ - Ian Dannapel <iansdannapel@...il.com>
+
+description: |
+ Efinix Trion and Titanium Series FPGAs support a method of loading the
+ bitstream over what is referred to as "SPI Passive Programming".
+ Only serial (1x bus width) is supported, setting the programming mode
+ is not in the scope the this manager and must be done elsewhere.
+
+ References:
+ - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
+ - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - efinix,trion-spi-passive
+ - efinix,titanium-spi-passive
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ spi-max-frequency:
+ maximum: 25000000
+
+ reg:
+ maxItems: 1
+
+ creset-gpios:
+ description:
+ reset and re-configuration trigger pin (low active)
+ maxItems: 1
+
+ cs-gpios:
+ description:
+ chip-select pin (low active)
+ maxItems: 1
+
+ cdone-gpios:
+ description:
+ optional configuration done status pin (high active)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - creset-gpios
+ - cs-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fpga_mgr_spi: fpga-mgr@0 {
+ compatible = "efinix,trion-spi-passive";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ spi-cpol;
+ creset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
--
2.34.1
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