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Message-Id: <20240630-a505-v3-1-ed1e8eae3d84@gmail.com>
Date: Sun, 30 Jun 2024 01:36:42 +0200
From: Barnabás Czémán <trabarni@...il.com>
To: Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Daniil Titov <daniilt971@...il.com>,
Barnabás Czémán <trabarni@...il.com>
Subject: [PATCH v3] drm/msm/adreno: Add support for Adreno 505 GPU
From: Daniil Titov <daniilt971@...il.com>
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz),
SDM439 (650 MHz).
Signed-off-by: Daniil Titov <daniilt971@...il.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Signed-off-by: Barnabás Czémán <trabarni@...il.com>
---
Changes in v3:
- Rebase on the latest linux-next.
- Link to v2: https://lore.kernel.org/r/20240604-a505-v2-1-dfa599a4d3c1@gmail.com
Changes in v2:
- use DRM_MSM_INACTIVE_PERIOD instead of 250 ms.
- Link to v1: https://lore.kernel.org/r/20240604-a505-v1-1-82ee1c04d200@gmail.com
---
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 13 +++++++++++++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 29 +++++++++++++++++------------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
3 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
index 455a953dee67..633f31539162 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
@@ -10,6 +10,19 @@
static const struct adreno_info a5xx_gpus[] = {
{
+ .chip_ids = ADRENO_CHIP_IDS(0x05000500),
+ .family = ADRENO_5XX,
+ .revn = 505,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_128K + SZ_8K),
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
+ ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ }, {
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
.family = ADRENO_5XX,
.revn = 506,
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c003f970189b..c0b5373e90d7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -439,7 +439,8 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
const struct adreno_five_hwcg_regs *regs;
unsigned int i, sz;
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu)) {
regs = a50x_hwcg;
sz = ARRAY_SIZE(a50x_hwcg);
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
@@ -483,7 +484,8 @@ static int a5xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x00000000);
/* Specify workarounds for various microcode issues */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a530(adreno_gpu)) {
/* Workaround for token end syncs
* Force a WFI after every direct-render 3D mode draw and every
* 2D mode 3 draw
@@ -752,10 +754,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
0x00100000 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
else
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
@@ -771,7 +774,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
}
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x100 << 11 | 0x100 << 22));
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
@@ -789,8 +793,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
* Disable the RB sampler datapath DP2 clock gating optimization
* for 1-SP GPUs, as it is enabled by default.
*/
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
+ adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
/* Disable UCHE global filter as SP can invalidate/flush independently */
@@ -1345,7 +1350,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
if (ret)
return ret;
- /* Adreno 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
+ /* Adreno 505, 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
/* Halt the sp_input_clk at HM level */
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055);
@@ -1388,9 +1393,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
u32 mask = 0xf;
int i, ret;
- /* A506, A508, A510 have 3 XIN ports in VBIF */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu))
+ /* A505, A506, A508, A510 have 3 XIN ports in VBIF */
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
mask = 0x7;
/* Clear the VBIF pipe before shutting down */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index cff8ce541d2c..2497bbc07ed4 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -324,6 +324,11 @@ static inline int adreno_is_a430(const struct adreno_gpu *gpu)
return adreno_is_revn(gpu, 430);
}
+static inline int adreno_is_a505(const struct adreno_gpu *gpu)
+{
+ return adreno_is_revn(gpu, 505);
+}
+
static inline int adreno_is_a506(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 506);
---
base-commit: 1eb586a9782cde8e5091b9de74603e0a8386b09e
change-id: 20240603-a505-e57389b61d2a
Best regards,
--
Barnabás Czémán <trabarni@...il.com>
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