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Message-ID: <CAN6iL-TdLdtoK2Cz4qyf6z8x=7c=Adzwi0GuC=-3CVeOzBZ_bA@mail.gmail.com>
Date: Tue, 2 Jul 2024 00:43:12 +0530
From: Pranjal Shrivastava <praan@...gle.com>
To: Rob Clark <robdclark@...il.com>
Cc: iommu@...ts.linux.dev, linux-arm-msm@...r.kernel.org, 
	Stephen Boyd <swboyd@...omium.org>, Robin Murphy <robin.murphy@....com>, 
	Rob Clark <robdclark@...omium.org>, Thierry Reding <thierry.reding@...il.com>, 
	Krishna Reddy <vdumpa@...dia.com>, Will Deacon <will@...nel.org>, Joerg Roedel <joro@...tes.org>, 
	Jason Gunthorpe <jgg@...pe.ca>, Jerry Snitselaar <jsnitsel@...hat.com>, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Georgi Djakov <quic_c_gdjako@...cinc.com>, 
	Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, 
	"open list:TEGRA IOMMU DRIVERS" <linux-tegra@...r.kernel.org>, 
	"moderated list:ARM SMMU DRIVERS" <linux-arm-kernel@...ts.infradead.org>, 
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields

On Mon, Jul 1, 2024 at 9:50 PM Rob Clark <robdclark@...il.com> wrote:
>
> From: Rob Clark <robdclark@...omium.org>
>
> For consistency, add the "CB" prefix to the bitfield defines for context
> registers.
>
> Signed-off-by: Rob Clark <robdclark@...omium.org>
> ---
>  drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c  |  2 +-
>  .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  | 18 +++----
>  drivers/iommu/arm/arm-smmu/arm-smmu.c         |  8 +--
>  drivers/iommu/arm/arm-smmu/arm-smmu.h         | 50 +++++++++----------
>  drivers/iommu/arm/arm-smmu/qcom_iommu.c       |  4 +-
>  5 files changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> index 957d988b6d83..4b2994b6126d 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> @@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
>         void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
>
>         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
> -       if (!(fsr & ARM_SMMU_FSR_FAULT))
> +       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
>                 return IRQ_NONE;
>
>         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> index 552199cbd9e2..e4ee78fb6a66 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> @@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma
>         writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
>
>         fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> -       if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) {
> +       if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) {
>                 u32 sctlr_orig, sctlr;
>
>                 /*
> @@ -298,7 +298,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
>         arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
>
>         fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> -       if (fsr & ARM_SMMU_FSR_FAULT) {
> +       if (fsr & ARM_SMMU_CB_FSR_FAULT) {
>                 /* Clear pending interrupts */
>                 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
> @@ -306,7 +306,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
>                  * TBU halt takes care of resuming any stalled transcation.
>                  * Kept it here for completeness sake.
>                  */
> -               if (fsr & ARM_SMMU_FSR_SS)
> +               if (fsr & ARM_SMMU_CB_FSR_SS)
>                         arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
>                                           ARM_SMMU_RESUME_TERMINATE);
>         }
> @@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
>                         phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
>
>                         fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> -                       if (fsr & ARM_SMMU_FSR_FAULT) {
> +                       if (fsr & ARM_SMMU_CB_FSR_FAULT) {
>                                 /* Clear pending interrupts */
>                                 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
> -                               if (fsr & ARM_SMMU_FSR_SS)
> +                               if (fsr & ARM_SMMU_CB_FSR_SS)
>                                         arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
>                                                           ARM_SMMU_RESUME_TERMINATE);
>                         }
> @@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
>                                       DEFAULT_RATELIMIT_BURST);
>
>         fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> -       if (!(fsr & ARM_SMMU_FSR_FAULT))
> +       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
>                 return IRQ_NONE;
>
>         fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> @@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
>
>         if (list_empty(&tbu_list)) {
>                 ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> -                                        fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> +                                        fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
>                 if (ret == -ENOSYS)
>                         dev_err_ratelimited(smmu->dev,
> @@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
>         phys_soft = ops->iova_to_phys(ops, iova);
>
>         tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> -                                fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> +                                fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>         if (!tmp || tmp == -EBUSY) {
>                 dev_dbg(smmu->dev,
>                         "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
> @@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
>                 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
>                 /* Retry or terminate any stalled transactions */
> -               if (fsr & ARM_SMMU_FSR_SS)
> +               if (fsr & ARM_SMMU_CB_FSR_SS)
>                         arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
>         }
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index 87c81f75cf84..23cf91ac409b 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -415,7 +415,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
>         int ret;
>
>         fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> -       if (!(fsr & ARM_SMMU_FSR_FAULT))
> +       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
>                 return IRQ_NONE;
>
>         fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> @@ -423,7 +423,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
>         cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
>
>         ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> -               fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> +               fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
>         if (ret == -ENOSYS)
>                 dev_err_ratelimited(smmu->dev,
> @@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
>                 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
>
>         reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR;
> -       if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE),
> +       if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE),
>                                       5, 50)) {
>                 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
>                 dev_err(dev,
> @@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
>         /* Make sure all context banks are disabled and clear CB_FSR  */
>         for (i = 0; i < smmu->num_context_banks; ++i) {
>                 arm_smmu_write_context_bank(smmu, i);
> -               arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> +               arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
>         }
>
>         /* Invalidate the TLB, just in case */
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index 4765c6945c34..b04a00126a12 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -196,34 +196,34 @@ enum arm_smmu_cbar_type {
>  #define ARM_SMMU_CB_PAR_F              BIT(0)
>
>  #define ARM_SMMU_CB_FSR                        0x58
> -#define ARM_SMMU_FSR_MULTI             BIT(31)
> -#define ARM_SMMU_FSR_SS                        BIT(30)
> -#define ARM_SMMU_FSR_UUT               BIT(8)
> -#define ARM_SMMU_FSR_ASF               BIT(7)
> -#define ARM_SMMU_FSR_TLBLKF            BIT(6)
> -#define ARM_SMMU_FSR_TLBMCF            BIT(5)
> -#define ARM_SMMU_FSR_EF                        BIT(4)
> -#define ARM_SMMU_FSR_PF                        BIT(3)
> -#define ARM_SMMU_FSR_AFF               BIT(2)
> -#define ARM_SMMU_FSR_TF                        BIT(1)
> -
> -#define ARM_SMMU_FSR_IGN               (ARM_SMMU_FSR_AFF |             \
> -                                        ARM_SMMU_FSR_ASF |             \
> -                                        ARM_SMMU_FSR_TLBMCF |          \
> -                                        ARM_SMMU_FSR_TLBLKF)
> -
> -#define ARM_SMMU_FSR_FAULT             (ARM_SMMU_FSR_MULTI |           \
> -                                        ARM_SMMU_FSR_SS |              \
> -                                        ARM_SMMU_FSR_UUT |             \
> -                                        ARM_SMMU_FSR_EF |              \
> -                                        ARM_SMMU_FSR_PF |              \
> -                                        ARM_SMMU_FSR_TF |              \
> -                                        ARM_SMMU_FSR_IGN)
> +#define ARM_SMMU_CB_FSR_MULTI          BIT(31)
> +#define ARM_SMMU_CB_FSR_SS             BIT(30)
> +#define ARM_SMMU_CB_FSR_UUT            BIT(8)
> +#define ARM_SMMU_CB_FSR_ASF            BIT(7)
> +#define ARM_SMMU_CB_FSR_TLBLKF         BIT(6)
> +#define ARM_SMMU_CB_FSR_TLBMCF         BIT(5)
> +#define ARM_SMMU_CB_FSR_EF             BIT(4)
> +#define ARM_SMMU_CB_FSR_PF             BIT(3)
> +#define ARM_SMMU_CB_FSR_AFF            BIT(2)
> +#define ARM_SMMU_CB_FSR_TF             BIT(1)
> +
> +#define ARM_SMMU_CB_FSR_IGN            (ARM_SMMU_CB_FSR_AFF |          \
> +                                        ARM_SMMU_CB_FSR_ASF |          \
> +                                        ARM_SMMU_CB_FSR_TLBMCF |       \
> +                                        ARM_SMMU_CB_FSR_TLBLKF)
> +
> +#define ARM_SMMU_CB_FSR_FAULT          (ARM_SMMU_CB_FSR_MULTI |        \
> +                                        ARM_SMMU_CB_FSR_SS |           \
> +                                        ARM_SMMU_CB_FSR_UUT |          \
> +                                        ARM_SMMU_CB_FSR_EF |           \
> +                                        ARM_SMMU_CB_FSR_PF |           \
> +                                        ARM_SMMU_CB_FSR_TF |           \
> +                                        ARM_SMMU_CB_FSR_IGN)
>
>  #define ARM_SMMU_CB_FAR                        0x60
>
>  #define ARM_SMMU_CB_FSYNR0             0x68
> -#define ARM_SMMU_FSYNR0_WNR            BIT(4)
> +#define ARM_SMMU_CB_FSYNR0_WNR         BIT(4)
>
>  #define ARM_SMMU_CB_FSYNR1             0x6c
>
> @@ -237,7 +237,7 @@ enum arm_smmu_cbar_type {
>  #define ARM_SMMU_CB_ATS1PR             0x800
>
>  #define ARM_SMMU_CB_ATSR               0x8f0
> -#define ARM_SMMU_ATSR_ACTIVE           BIT(0)
> +#define ARM_SMMU_CB_ATSR_ACTIVE                BIT(0)
>
>  #define ARM_SMMU_RESUME_TERMINATE      BIT(0)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index e079bb7a993e..b98a7a598b89 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
>
>         fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
>
> -       if (!(fsr & ARM_SMMU_FSR_FAULT))
> +       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
>                 return IRQ_NONE;
>
>         fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
> @@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
>
>                 /* Clear context bank fault address fault status registers */
>                 iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
> -               iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> +               iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
>
>                 /* TTBRs */
>                 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
> --
> 2.45.2
>
Reviewed-by: Pranjal Shrivastava <praan@...gle.com>

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