linux-kernel - Re: [PATCH v7] dt-bindings: PCI: altera: Convert to YAML

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Date: Mon, 1 Jul 2024 15:19:31 -0700 (PDT)
From: matthew.gerlach@...ux.intel.com
To: Conor Dooley <conor@...nel.org>
cc: lpieralisi@...nel.org, kw@...ux.com, robh@...nel.org, bhelgaas@...gle.com, 
    krzk+dt@...nel.org, conor+dt@...nel.org, joyce.ooi@...el.com, 
    linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
    linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7] dt-bindings: PCI: altera: Convert to YAML



On Thu, 27 Jun 2024, Conor Dooley wrote:

> Been stalling replying here, was wondering if Rob would look given he
> reviewed the previous versions.
>
> On Fri, Jun 14, 2024 at 11:35:20AM -0500, matthew.gerlach@...ux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>>
>> Convert the device tree bindings for the Altera Root Port PCIe controller
>> from text to YAML. Update the entries in the interrupt-map field to have
>> the correct number of address cells for the interrupt parent.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
>> deleted file mode 100644
>> index 816b244a221e..000000000000
>> --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
>> +++ /dev/null
>> @@ -1,50 +0,0 @@
>> -* Altera PCIe controller
>> -
>> -Required properties:
>> -- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
>> -- reg:		a list of physical base address and length for TXS and CRA.
>> -		For "altr,pcie-root-port-2.0", additional HIP base address and length.
>> -- reg-names:	must include the following entries:
>> -		"Txs": TX slave port region
>> -		"Cra": Control register access region
>
>> -		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
>
> I think this should be constrained in the new yaml binding by setting
> maxItems: for reg/reg-names to 2 for 1.0 and, if I am not
> misunderstanding what "must include" means, minItems: to 3 for 2.0.

Your understanding is correct. Your suggestion makes the binding more 
precise, and I will implement it in v8.

Thanks for the feedback,

Matthew Gerlach

>
> Thanks,
> Conor.
>
>> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> new file mode 100644
>> index 000000000000..0aaf5dbcc9cc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> @@ -0,0 +1,93 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2015, 2019, 2024, Intel Corporation
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera PCIe Root Port
>> +
>> +maintainers:
>> +  - Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - altr,pcie-root-port-1.0
>> +      - altr,pcie-root-port-2.0
>> +
>> +  reg:
>> +    items:
>> +      - description: TX slave port region
>> +      - description: Control register access region
>> +      - description: Hard IP region
>> +    minItems: 2
>> +
>> +  reg-names:
>> +    items:
>> +      - const: Txs
>> +      - const: Cra
>> +      - const: Hip
>> +    minItems: 2
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  interrupt-map-mask:
>> +    items:
>> +      - const: 0
>> +      - const: 0
>> +      - const: 0
>> +      - const: 7
>> +
>> +  interrupt-map:
>> +    maxItems: 4
>> +
>> +  "#interrupt-cells":
>> +    const: 1
>> +
>> +  msi-parent: true
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - interrupts
>> +  - "#interrupt-cells"
>> +  - interrupt-controller
>> +  - interrupt-map
>> +  - interrupt-map-mask
>> +
>> +allOf:
>> +  - $ref: /schemas/pci/pci-host-bridge.yaml#
>