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Message-Id: <20240701112317.94022-1-baolu.lu@linux.intel.com>
Date: Mon, 1 Jul 2024 19:23:15 +0800
From: Lu Baolu <baolu.lu@...ux.intel.com>
To: Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Jason Gunthorpe <jgg@...pe.ca>,
Kevin Tian <kevin.tian@...el.com>
Cc: iommu@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Lu Baolu <baolu.lu@...ux.intel.com>
Subject: [PATCH v3 0/2] iommu/vt-d: Refactor PRI enable/disable steps
The page fault handling framework within the iommu core has defined the
PRI enable and disable flows in the comments for the
iopf_queue_remove_device() interface. This series aims to refactor the
PRI enable/disable steps in the Intel iommu driver to align with these
definitions.
Change log:
v3:
- Refine the lock requirement. Only assert the lock when it is
required.
v2:
- https://lore.kernel.org/linux-iommu/20240627023121.50166-1-baolu.lu@linux.intel.com/
- The cache invalidation for a context entry change should not affect
the devices not related to the entry. Fix this by always using
device-selective cache invalidation.
v1:
- https://lore.kernel.org/linux-iommu/20240606034019.42795-1-baolu.lu@linux.intel.com/
Lu Baolu (2):
iommu/vt-d: Add helper to flush caches for context change
iommu/vt-d: Refactor PCI PRI enabling/disabling callbacks
drivers/iommu/intel/iommu.h | 13 +++++
drivers/iommu/intel/iommu.c | 89 +++++++++++++++++------------
drivers/iommu/intel/pasid.c | 108 +++++++++++++++++++++++++++++-------
3 files changed, 153 insertions(+), 57 deletions(-)
--
2.34.1
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