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Message-ID: <20240701-line-congress-f838a8b6b1e7@spud>
Date: Mon, 1 Jul 2024 13:25:06 +0100
From: Conor Dooley <conor@...nel.org>
To: Yixun Lan <dlan@...too.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Samuel Holland <samuel.holland@...ive.com>,
Anup Patel <anup@...infault.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Lubomir Rintel <lkundrak@...sk>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...ive.com>, linux-riscv@...ts.infradead.org,
linux-serial@...r.kernel.org, Inochi Amaoto <inochiama@...look.com>,
Meng Zhang <zhangmeng.kevin@...cemit.com>,
Yangyu Chen <cyy@...self.name>
Subject: Re: [PATCH v2 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
On Thu, Jun 27, 2024 at 03:31:16PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@...self.name>
>
> The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
> SoC.
>
> Link: https://www.spacemit.com/en/spacemit-x60-core/
>
Same comment as v1 here :) With that addressed,
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
> Signed-off-by: Yangyu Chen <cyy@...self.name>
> Signed-off-by: Yixun Lan <dlan@...too.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d87dd50f1a4b5..5ad9cb4103356 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,6 +46,7 @@ properties:
> - sifive,u7
> - sifive,u74
> - sifive,u74-mc
> + - spacemit,x60
> - thead,c906
> - thead,c910
> - thead,c920
>
> --
> 2.45.2
>
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