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Message-ID: <14a7db3a-663a-4e3f-b29c-a733e98efc32@linux.intel.com>
Date: Tue, 2 Jul 2024 09:47:36 +0800
From: Baolu Lu <baolu.lu@...ux.intel.com>
To: "Tian, Kevin" <kevin.tian@...el.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
Jason Gunthorpe <jgg@...pe.ca>
Cc: baolu.lu@...ux.intel.com, "iommu@...ts.linux.dev"
<iommu@...ts.linux.dev>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/2] iommu/vt-d: Add helper to flush caches for context
change
On 7/2/24 9:11 AM, Tian, Kevin wrote:
>> From: Lu Baolu<baolu.lu@...ux.intel.com>
>> Sent: Monday, July 1, 2024 7:23 PM
>> +
>> + /*
>> + * For scalable mode:
>> + * - Domain-selective PASID-cache invalidation to affected domains
>> + * - Domain-selective IOTLB invalidation to affected domains
>> + * - Global Device-TLB invalidation to affected functions
>> + */
>> + if (flush_domains) {
>> + /*
>> + * If the IOMMU is running in scalable mode and there might
>> + * be potential PASID translations, the caller should hold
>> + * the lock to ensure that context changes and cache flushes
>> + * are atomic.
>> + */
>> + assert_spin_locked(&iommu->lock);
>> + for (i = 0; i < info->pasid_table->max_pasid; i++) {
>> + pte = intel_pasid_get_entry(info->dev, i);
>> + if (!pte || !pasid_pte_is_present(pte))
>> + continue;
>> +
>> + did = pasid_get_domain_id(pte);
>> + qi_flush_pasid_cache(iommu, did,
>> QI_PC_ALL_PASIDS, 0);
>> + iommu->flush.flush_iotlb(iommu, did, 0, 0,
>> DMA_TLB_DSI_FLUSH);
>> + }
>> + }
>> +
>> + __context_flush_dev_iotlb(info);
>> +}
> this only invalidates devtlb w/o PASID. We miss a pasid devtlb invalidation
> with global bit set.
I am not sure about this. The spec says "Global Device-TLB invalidation
to affected functions", I am not sure whether this implies any PASID-
based-Device-TLB invalidation.
If so, perhaps we need a separated fix to address this.
Best regards,
baolu
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