linux-kernel - Re: [PATCH 0/7] Add PCIe support for bcm2712

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Message-ID: <34701ce5-4f35-463d-a2d2-5144a20aaf0f@suse.de>
Date: Tue, 2 Jul 2024 13:05:15 +0300
From: Stanimir Varbanov <svarbanov@...e.de>
To: Florian Fainelli <florian.fainelli@...adcom.com>,
 Stanimir Varbanov <svarbanov@...e.de>, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-rpi-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
 Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Jim Quinlan <jim2101024@...il.com>,
 Nicolas Saenz Julienne <nsaenz@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>, kw@...ux.com,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Andrea della Porta <andrea.porta@...e.com>,
 Phil Elwell <phil@...pberrypi.com>, Jonathan Bell <jonathan@...pberrypi.com>
Subject: Re: [PATCH 0/7] Add PCIe support for bcm2712

Hi Florian,

On 6/26/24 14:31, Florian Fainelli wrote:
> Hi,
> 
> On 26/06/2024 11:45, Stanimir Varbanov wrote:
>> This patchset aims to add bare minimum support for bcm2712
>> in brcmstb PCIe driver needed to support the peripherals from
>> RP1 south-bridge found in RPi5. In order to support RP1
>> PCIe endpoint peripherals a new interrupt controller is added.
>> The interrupt controller supports 64 interrupt sources which
>> are enough to handle 61 RP1 peripherals.
>>
>> Patch 1 is adding DT binding schema for the MIP interrupt
>> controller, patch 2 is adding relevant changes for PCIe
>> bcm2712 in yaml. Patch 3 adds MIP intterrupt cotroller driver.
>> Patches 4 and 5 are preparations for adding bcm2712 support in 6.
>> The last patch updates bcm2712 .dsti by adding pcie DT nodes.
>>
>> Few concerns about the implementation:
>>   - the connection between MIP interrupt-controller and PCIe RC is
>>     done through BAR1. The PCIe driver is parsing the msi_parent
>>     DT property in order to obtain few private DT properties like
>>     "brcm,msi-pci-addr" and "reg". IMO this looks hackish but I failed
>>     to find something better. Ideas?
>>
>>   - in downstream RPi kernel "ranges" and "dma-ranges" DT properties
>>     are under an axi {} simple-bus node even that PCIe block is on CPU
>>     MMIO bus. I tried to merge axi {} in soc {} and the result could be
>>     seen on the last patch in this series, but I'm still not sure that
>>     it looks good enough.
>>
>> This series has been functionally tested on OpenSUSE Tumbleweed with
>> downstream RP1 south-bridge PCIe endpoint driver implementation as
>> MFD by using ethernet which is part of it.
>>
>> The series is based on Andrea's "Add minimal boot support for
>> Raspberry Pi 5"
>> series.
>>
>> Comments are welcome!
> 
> We are just about submitting support for 7712 which is the sister chip
> of 2712 and requires similar, if not identical types of changes to
> pcie-brcmstb.c, would you mind reviewing that patch series when it gets
> posted by Jim in the next few days, and base yours upon that one? It

Sure, I'll review bcm7712 series and rebase bcm2712 on top of it.

> does separate changes in a more atomic and a more reviewer friendly
> rather than having one big commit modifying pcie-brcmstb.c

Agreed.

> 
> Thanks.

~Stan