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Message-ID: <gx3vhkjvwwzxvbh36c3bwp5kw7pxiki2rvsp7ig6rdo3gw6fju@afmhwuwdqquj>
Date: Wed, 3 Jul 2024 13:01:38 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Abhishek Sahu <absahu@...eaurora.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Stephen Boyd <sboyd@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>, stable@...r.kernel.org
Subject: Re: [PATCH v2 1/6] clk: qcom: alpha-pll: Fix the pll post div mask
and shift
On Tue, Jul 02, 2024 at 09:20:39PM GMT, Satya Priya Kakitapalli wrote:
> The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
> Also, correct the pll postdiv shift used in trion pll postdiv
> set rate API. The shift value is not same for different types of
> plls and should be taken from the pll's .post_div_shift member.
Two separate commits for two different fixes, please.
>
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Cc: stable@...r.kernel.org
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 8a412ef47e16..6107c144c0f5 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -40,7 +40,7 @@
>
> #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
> # define PLL_POST_DIV_SHIFT 8
> -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
> +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
> # define PLL_ALPHA_EN BIT(24)
> # define PLL_ALPHA_MODE BIT(25)
> # define PLL_VCO_SHIFT 20
> @@ -1496,8 +1496,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
> }
>
> return regmap_update_bits(regmap, PLL_USER_CTL(pll),
> - PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
> - val << PLL_POST_DIV_SHIFT);
> + PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
> + val << pll->post_div_shift);
> }
>
> const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
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