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Message-Id: <20240703095712.64202-15-dapeng1.mi@linux.intel.com>
Date: Wed, 3 Jul 2024 09:57:08 +0000
From: Dapeng Mi <dapeng1.mi@...ux.intel.com>
To: Sean Christopherson <seanjc@...gle.com>,
Paolo Bonzini <pbonzini@...hat.com>
Cc: kvm@...r.kernel.org,
linux-kernel@...r.kernel.org,
Jim Mattson <jmattson@...gle.com>,
Mingwei Zhang <mizhang@...gle.com>,
Xiong Zhang <xiong.y.zhang@...el.com>,
Zhenyu Wang <zhenyuw@...ux.intel.com>,
Like Xu <like.xu.linux@...il.com>,
Jinrong Liang <cloudliang@...cent.com>,
Dapeng Mi <dapeng1.mi@...el.com>,
Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: [Patch v5 14/18] x86: pmu: Adjust lower boundary of llc-misses event to 0 for legacy CPUs
For these legacy Intel CPUs without clflush/clflushopt support, there is
on way to force to trigger a LLC miss and the measured llc misses is
possible to be 0. Thus adjust the lower boundary of llc-misses event to
0 to avoid possible false positive.
Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
---
x86/pmu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/x86/pmu.c b/x86/pmu.c
index 799d8d5c..c9c5fc19 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -82,6 +82,7 @@ struct pmu_event {
enum {
INTEL_INSTRUCTIONS_IDX = 1,
INTEL_REF_CYCLES_IDX = 2,
+ INTEL_LLC_MISSES_IDX = 4,
INTEL_BRANCHES_IDX = 5,
};
@@ -877,6 +878,15 @@ int main(int ac, char **av)
gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]);
instruction_idx = INTEL_INSTRUCTIONS_IDX;
branch_idx = INTEL_BRANCHES_IDX;
+
+ /*
+ * For legacy Intel CPUS without clflush/clflushopt support,
+ * there is no way to force to trigger a LLC miss, thus set
+ * the minimum value to 0 to avoid false positives.
+ */
+ if (!this_cpu_has(X86_FEATURE_CLFLUSH))
+ gp_events[INTEL_LLC_MISSES_IDX].min = 0;
+
report_prefix_push("Intel");
set_ref_cycle_expectations();
} else {
--
2.40.1
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