[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <alpine.DEB.2.21.2407042324300.38148@angie.orcam.me.uk>
Date: Thu, 4 Jul 2024 23:36:02 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Jiaxun Yang <jiaxun.yang@...goat.com>
cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Florian Fainelli <florian.fainelli@...adcom.com>,
Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
Huacai Chen <chenhuacai@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
Serge Semin <fancer.lancer@...il.com>,
"paulburton@...nel.org" <paulburton@...nel.org>,
"linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/10] MIPS: smp: Make IPI interrupts scalable
On Thu, 4 Jul 2024, Jiaxun Yang wrote:
> > SOC-it (or SOC-it 101 to be precise) is the name of a bus controller:
> >
> > System controller/revision = MIPS SOC-it 101 OCP / 1.3 SDR-FW-4:1
> >
> > used across numerous platforms from the M4K core onwards, UP, MT, or MP.
> > I think it would make sense if you revealed the processor type instead.
>
> Sure, sorry to be vague on the platform detail.
>
> I actually tried on two Malta configurations, CoreFPGA6 interAptiv 2MPF (2 cores, 2 VPE, 4TC),
> and CoreFPGA3 34Kc MT (2VPE 9TC).
This is much better, thanks, and the choice of CPUs feels adequate. The
mention of the 34K CPU brings fond memories too, as I was a member of the
development team for this design, very innovative at its time, and still
nowadays I believe.
> > Technically I could run it on my SB1250, but I'm too overloaded now to
> > commit to any timescale. Sorry.
>
> No worries, I'll try to fetch a BMIPS3000 SMP router to get Broadcom platform
> undercover.
But that's a completely different design from the SB-1 line, isn't it?
Maciej
Powered by blists - more mailing lists