[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZoavUGcYLULHpVfg@arm.com>
Date: Thu, 4 Jul 2024 15:18:56 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Mark Brown <broonie@...nel.org>
Cc: Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Fuad Tabba <tabba@...gle.com>, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev
Subject: Re: [PATCH v2 2/4] arm64/fpsimd: Discover maximum vector length
implemented by any CPU
On Thu, Jun 06, 2024 at 04:21:44PM +0100, Mark Brown wrote:
> When discovering the vector lengths for SVE and SME we do not currently
> record the maximum VL supported on any individual CPU. This is expected
> to be the same for all CPUs but the architecture allows asymmetry, if we
> do encounter an asymmetric system then some CPUs may support VLs higher
> than the maximum Linux will use. Since the pKVM hypervisor needs to
> support saving and restoring anything the host can physically set it
> needs to know the maximum value any CPU could have, add support for
> enumerating it and validation for late CPUs.
>
> Signed-off-by: Mark Brown <broonie@...nel.org>
Acked-by: Catalin Marinas <catalin.marinas@....com>
I guess the %lu suggested by Fuad can be done when applying the patch.
Powered by blists - more mailing lists