linux-kernel - Re: [PATCH v4 2/3] LoongArch: KVM: Add LBT feature detection function

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <554b10e8-a7ab-424a-f987-ea679859a220@loongson.cn>
Date: Fri, 5 Jul 2024 09:21:18 +0800
From: maobibo <maobibo@...ngson.cn>
To: Jiaxun Yang <jiaxun.yang@...goat.com>, Huacai Chen <chenhuacai@...nel.org>
Cc: Tianrui Zhao <zhaotianrui@...ngson.cn>, WANG Xuerui <kernel@...0n.name>,
 kvm@...r.kernel.org, loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/3] LoongArch: KVM: Add LBT feature detection function



On 2024/7/5 上午3:44, Jiaxun Yang wrote:
> 
> 
> On 2024/7/4 09:35, maobibo wrote:
>> In another thread I found that Jiaxun said he has a solution to make
>>> LBT be a vcpu feature and still works well. However, that may take
>>> some time and is too late for 6.11.
>>>
>>> But we have another choice now: just remove the UAPI and vm.c parts in
>>> this series, let the LBT main parts be upstream in 6.11, and then
>>> solve other problems after 6.11. Even if Jiaxun's solution isn't
>>> usable, we can still use this old vm feature solution then.
> 
> IMO this is the best approach to make some progress.
> 
>>
>> I am sure it is best if it is VM feature for LBT feature detection, 
>> LSX/LASX feature detection uses CPU feature, we can improve it later.
> 
> Please justify the reason, we should always be serious on UAPI design 
> choices.
> I don't really understand why the approach worked so well on Arm & 
> RISC-V is not working
> for you.
On the other hand, can you list benefits or disadvantage of approaches 
on different architecture?

Or you post patch about host cpu support, I list its disadvantage. Or I 
post patch about host cpu support with scheduled time, then we talk 
about it. Is that fair for you?

It is unfair that you list some approaches and let others spend time to 
do, else you are my top boss :)
> 
> I understand you may have some plans in your mind, please elaborate so 
> we can smash
> them together. That's how community work.
> 
>>
>> For host cpu type or migration feature detection, I have no idea now, 
>> also I do not think it will be big issue for me, I will do it with 
>> scheduled time. Of source, welcome Jiaxun and you to implement host 
>> cpu type or migration feature detection.
> 
> My concern is if you allow CPU features to have "auto" property you are 
> risking create
> inconsistency among migration. Once you've done that it's pretty hard to 
> get rid of it.
> 
> Please check how RISC-V dealing with CPU features at QMP side.
> 
> I'm not meant to hinder your development work, but we should always 
> think ahead.
Yes, it is potential issue and we will solve it. Another potential issue 
is that PV features may different on host, you cannot disable PV 
features directly.  The best way is that you post patch about it, then 
we can talk about together, else it may be kindly reminder, also may be 
waste of time, everyone is busy working for boss :)

Regards
Bibo Mao
> 
> Thanks
> - Jiaxun
>>