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Message-ID: <d25c2dbb-f862-4f06-acb7-a3e7ebe954db@linaro.org>
Date: Fri, 5 Jul 2024 11:08:18 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jie Gan <quic_jiegan@...cinc.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Mike Leach <mike.leach@...aro.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
James Clark <james.clark@....com>
Cc: Jinlong Mao <quic_jinlmao@...cinc.com>, Leo Yan <leo.yan@...aro.org>,
coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Tao Zhang <quic_taozha@...cinc.com>, Trilok Soni <quic_tsoni@...cinc.com>,
Song Chai <quic_songchai@...cinc.com>, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: Add CCU and ETR nodes for
SA8775p
On 05/07/2024 11:00, Jie Gan wrote:
> Add CCU and ETR device tree nodes to enable related functions.
>
> Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 163 ++++++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 23f1b2e5e624..ef4df5e59ab3 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -1664,6 +1664,38 @@ ice: crypto@...8000 {
> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> };
>
> + ccu@...1000 {
> + compatible = "qcom,coresight-ccu";
> + reg = <0x0 0x4001000 0x0 0x1000>;
> + reg-names = "ccu-base";
NAK, not tested.
Follow your own internal guidelines - they are precise in what testing
you must peform.
Best regards,
Krzysztof
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