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Message-ID: <20240705021110.2495344-1-sunyeal.hong@samsung.com>
Date: Fri,  5 Jul 2024 11:11:05 +0900
From: Sunyeal Hong <sunyeal.hong@...sung.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, Sylwester Nawrocki
	<s.nawrocki@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar
	<alim.akhtar@...sung.com>, Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org, Sunyeal Hong <sunyeal.hong@...sung.com>
Subject: [PATCH 0/5] initial clock support for exynosauto v920 SoC

This patchset adds initial clock driver support for Exynos Auto v920 SoC.
This driver uses HW Auto Clock gating. So all gate clocks did not register.

Below CMU blocks are supported in this patchset and remains will be
implemented later.

- CMU_TOP
- CMU_PERIC0

Sunyeal Hong (5):
  dt-bindings: clock: add Exynos Auto v920 SoC CMU bindings
  dt-bindings: clock: add clock binding definitions for Exynos Auto v920
  arm64: dts: exynos: add initial CMU clock nodes in Exynos Auto v920
  clk: samsung: clk-pll: Add support for pll_531x
  clk: samsung: add top clock support for Exynos Auto v920 SoC

 .../clock/samsung,exynosautov920-clock.yaml   |  115 ++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |   40 +-
 drivers/clk/samsung/Makefile                  |    1 +
 drivers/clk/samsung/clk-exynosautov920.c      | 1176 +++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |   45 +
 drivers/clk/samsung/clk-pll.h                 |    1 +
 .../clock/samsung,exynosautov920.h            |  191 +++
 7 files changed, 1556 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
 create mode 100644 drivers/clk/samsung/clk-exynosautov920.c
 create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h

-- 
2.43.2


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