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Message-ID: <20240705153252.1571814-2-quic_mojha@quicinc.com>
Date: Fri, 5 Jul 2024 21:02:52 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: <lee@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Mukesh Ojha <quic_mojha@...cinc.com>
Subject: [PATCH 2/2] arm64: dts: qcom: sa8775p: Add TCSR halt register space

Enable download mode for sa8775p which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@...cinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23f1b2e5e624..a46d00b1ddda 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -221,6 +221,7 @@ eud_in: endpoint {
 	firmware {
 		scm {
 			compatible = "qcom,scm-sa8775p", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
 			memory-region = <&tz_ffi_mem>;
 		};
 	};
@@ -2824,6 +2825,11 @@ tcsr_mutex: hwlock@...0000 {
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@...0000 {
+			compatible = "qcom,sa8775p-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
 		gpucc: clock-controller@...0000 {
 			compatible = "qcom,sa8775p-gpucc";
 			reg = <0x0 0x03d90000 0x0 0xa000>;
-- 
2.34.1


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