| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <202407070606.q2TZuFwp-lkp@intel.com>
Date: Sun, 7 Jul 2024 07:05:11 +0800
From: kernel test robot <lkp@...el.com>
To: Jiaxun Yang <jiaxun.yang@...goat.com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Florian Fainelli <florian.fainelli@...adcom.com>,
Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
Huacai Chen <chenhuacai@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Serge Semin <fancer.lancer@...il.com>,
Paul Burton <paulburton@...nel.org>
Cc: oe-kbuild-all@...ts.linux.dev, linux-mips@...r.kernel.org,
linux-kernel@...r.kernel.org, Jiaxun Yang <jiaxun.yang@...goat.com>
Subject: Re: [PATCH v2 06/10] irqchip: irq-mips-gic: Switch to ipi_mux
Hi Jiaxun,
kernel test robot noticed the following build errors:
[auto build test ERROR on 0b58e108042b0ed28a71cd7edf5175999955b233]
url: https://github.com/intel-lab-lkp/linux/commits/Jiaxun-Yang/MIPS-smp-Make-IPI-interrupts-scalable/20240706-040839
base: 0b58e108042b0ed28a71cd7edf5175999955b233
patch link: https://lore.kernel.org/r/20240705-b4-mips-ipi-improvements-v2-6-2d50b56268e8%40flygoat.com
patch subject: [PATCH v2 06/10] irqchip: irq-mips-gic: Switch to ipi_mux
config: mips-allnoconfig (https://download.01.org/0day-ci/archive/20240707/202407070606.q2TZuFwp-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240707/202407070606.q2TZuFwp-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407070606.q2TZuFwp-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/irqchip/irq-mips-gic.c:27:
arch/mips/include/asm/ipi.h:54:6: warning: no previous prototype for 'mips_smp_ipi_set_virq_range' [-Wmissing-prototypes]
54 | void mips_smp_ipi_set_virq_range(int virq, int nr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/mips/include/asm/ipi.h:58:6: warning: no previous prototype for 'mips_smp_ipi_set_irqdomain' [-Wmissing-prototypes]
58 | void mips_smp_ipi_set_irqdomain(struct irq_domain *d)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/irqchip/irq-mips-gic.c: In function 'gic_of_init':
>> drivers/irqchip/irq-mips-gic.c:751:15: error: too many arguments to function 'gic_ipi_mux_init'
751 | ret = gic_ipi_mux_init(node, gic_irq_domain);
| ^~~~~~~~~~~~~~~~
drivers/irqchip/irq-mips-gic.c:642:19: note: declared here
642 | static inline int gic_ipi_mux_init(struct device_node *node)
| ^~~~~~~~~~~~~~~~
vim +/gic_ipi_mux_init +751 drivers/irqchip/irq-mips-gic.c
663
664 static int __init gic_of_init(struct device_node *node,
665 struct device_node *parent)
666 {
667 unsigned int cpu_vec, i, gicconfig;
668 unsigned long reserved;
669 phys_addr_t gic_base;
670 struct resource res;
671 size_t gic_len;
672 int ret;
673
674 /* Find the first available CPU vector. */
675 i = 0;
676 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
677 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
678 i++, &cpu_vec))
679 reserved |= BIT(cpu_vec);
680
681 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
682 if (cpu_vec == hweight_long(ST0_IM)) {
683 pr_err("No CPU vectors available\n");
684 return -ENODEV;
685 }
686
687 if (of_address_to_resource(node, 0, &res)) {
688 /*
689 * Probe the CM for the GIC base address if not specified
690 * in the device-tree.
691 */
692 if (mips_cm_present()) {
693 gic_base = read_gcr_gic_base() &
694 ~CM_GCR_GIC_BASE_GICEN;
695 gic_len = 0x20000;
696 pr_warn("Using inherited base address %pa\n",
697 &gic_base);
698 } else {
699 pr_err("Failed to get memory range\n");
700 return -ENODEV;
701 }
702 } else {
703 gic_base = res.start;
704 gic_len = resource_size(&res);
705 }
706
707 if (mips_cm_present()) {
708 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
709 /* Ensure GIC region is enabled before trying to access it */
710 __sync();
711 }
712
713 mips_gic_base = ioremap(gic_base, gic_len);
714 if (!mips_gic_base) {
715 pr_err("Failed to ioremap gic_base\n");
716 return -ENOMEM;
717 }
718
719 gicconfig = read_gic_config();
720 gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig);
721 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
722
723 if (cpu_has_veic) {
724 /* Always use vector 1 in EIC mode */
725 gic_cpu_pin = 0;
726 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
727 __gic_irq_dispatch);
728 } else {
729 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
730 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
731 gic_irq_dispatch);
732 }
733
734 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
735 gic_shared_intrs, 0,
736 &gic_irq_domain_ops, NULL);
737 if (!gic_irq_domain) {
738 pr_err("Failed to add IRQ domain");
739 return -ENXIO;
740 }
741
742 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
743
744 /* Setup defaults */
745 for (i = 0; i < gic_shared_intrs; i++) {
746 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
747 change_gic_trig(i, GIC_TRIG_LEVEL);
748 write_gic_rmask(i);
749 }
750
> 751 ret = gic_ipi_mux_init(node, gic_irq_domain);
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Powered by blists - more mailing lists