linux-kernel - Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine

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Message-ID: <ea8a5f78-65a5-4be8-9e15-57351a839f52@nxp.com>
Date: Mon, 8 Jul 2024 14:47:23 +0800
From: Liu Ying <victor.liu@....com>
To: Krzysztof Kozlowski <krzk@...nel.org>, dri-devel@...ts.freedesktop.org,
 devicetree@...r.kernel.org, imx@...ts.linux.dev,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: p.zabel@...gutronix.de, airlied@...il.com, daniel@...ll.ch,
 maarten.lankhorst@...ux.intel.com, mripard@...nel.org, tzimmermann@...e.de,
 robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
 festevam@...il.com, tglx@...utronix.de
Subject: Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display
 Controller pixel engine

On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller pixel engine consists of all processing units
>> that operate in the AXI bus clock domain.  Command sequencer and interrupt
>> controller of the Display Controller work with AXI bus clock, but they are
>> not in pixel engine.
>>
>> Signed-off-by: Liu Ying <victor.liu@....com>
>> ---
> 
> 
>> +
>> +        extdst@...80a40 {
>> +            compatible = "fsl,imx8qxp-dc-extdst";
>> +            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>> +            reg-names = "pec", "cfg";
>> +            interrupt-parent = <&dc0_intc>;
>> +            interrupts = <12>, <13>, <14>;
>> +            interrupt-names = "shdload", "framecomplete", "seqcomplete";
>> +            fsl,dc-ed-id = <5>;
>> +        };
>> +
>> +        fetchwarp@...80a60 {
>> +            compatible = "fsl,imx8qxp-dc-fetchwarp";
>> +            reg = <0x56180a60 0x4>, <0x56186400 0x400>;
> 
> Aha, one word for address range.

Sorry, I don't get your idea here.

> 
> Sorry, these are not separate devices.

Hmm, again, Maxime suggested to use separate devices.

> 
> Best regards,
> Krzysztof
> 
> 

-- 
Regards,
Liu Ying