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Message-ID: <c2a810b1-2926-4b4b-8939-e93b4f3673fe@linaro.org>
Date: Mon, 8 Jul 2024 14:38:39 +0200
From: neil.armstrong@...aro.org
To: Zhaoxiong Lv <lvzhaoxiong@...qin.corp-partner.google.com>,
 robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 airlied@...il.com, daniel@...ll.ch, mripard@...nel.org, dianders@...gle.com,
 hsinyi@...gle.com, awarnecke002@...mail.com, quic_jesszhan@...cinc.com,
 dmitry.baryshkov@...aro.org
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 5/5] drm/panel: :boe-th101mb31ig002: Support for
 starry-er88577 MIPI-DSI panel

On 04/07/2024 09:29, Zhaoxiong Lv wrote:
> The init_code of the starry-er88577 panel is very similar to the
> panel-boe-th101mb31ig002-28a.c driver, so we make it compatible with
> the panel-boe-th101mb31ig002-28a.c driver
> 
> Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@...qin.corp-partner.google.com>
> ---
> Changes between V5 and V4:
> -  1. Compatible with starry-er88577 panel in panel-boe-th101mb31ig002-28a.c driver,.
> v4: https://lore.kernel.org/all/20240620115245.31540-3-lvzhaoxiong@huaqin.corp-partner.google.com/
> 
> Changes between V4 and V3:
> -  1. Adjust the ".clock" assignment format.
> v3: https://lore.kernel.org/all/20240614145609.25432-3-lvzhaoxiong@huaqin.corp-partner.google.com/
> 
> Changes between V3 and V2:
> -  Separate Starry-er88577 from the panel-kingdisplay-kd101ne3 driver.
> -  Use mipi_dsi_dcs_set_display_on_multi().
> -  Use mipi_dsi_dcs_exit_sleep_mode_multi() and mipi_dsi_msleep().
> v2: https://lore.kernel.org/all/20240601084528.22502-5-lvzhaoxiong@huaqin.corp-partner.google.com/
> 
> Changes between V2 and V1:
> -  Add compatible for Starry er88577 in panel-kingdisplay-kd101ne3 drivers.
> 
> ---
>   .../drm/panel/panel-boe-th101mb31ig002-28a.c  | 119 ++++++++++++++++++
>   1 file changed, 119 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c
> index 736bfba607cf..c103236cc970 100644
> --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c
> +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c
> @@ -25,6 +25,12 @@ struct panel_desc {
>   	enum mipi_dsi_pixel_format format;
>   	int (*init)(struct boe_th101mb31ig002 *ctx);
>   	unsigned int lanes;
> +	bool lp11_before_reset;
> +	unsigned int vcioo_to_lp11_delay_ms;
> +	unsigned int lp11_to_reset_delay_ms;
> +	unsigned int backlight_off_to_display_off_delay_ms;
> +	unsigned int enter_sleep_to_reset_down_delay_ms;
> +	unsigned int power_off_delay_ms;
>   };
>   
>   struct boe_th101mb31ig002 {
> @@ -108,6 +114,65 @@ static int boe_th101mb31ig002_enable(struct boe_th101mb31ig002 *ctx)
>   	return dsi_ctx.accum_err;
>   }
>   
> +static int starry_er88577_init_cmd(struct boe_th101mb31ig002 *ctx)
> +{
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> +
> +	msleep(70);
> +
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10,
> +					       0x00);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x40);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x61, 0x4f, 0x42, 0x3e, 0x2d,
> +					       0x31, 0x1a, 0x33, 0x33, 0x33, 0x52, 0x40,
> +					       0x47, 0x38, 0x34, 0x26, 0x0e, 0x06, 0x7c,
> +					       0x61, 0x4f, 0x42, 0x3e, 0x2d, 0x31, 0x1a,
> +					       0x33, 0x33, 0x33, 0x52, 0x40, 0x47, 0x38,
> +					       0x34, 0x26, 0x0e, 0x06);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0xcc, 0x76, 0x12, 0x34, 0x44, 0x44,
> +					       0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0f,
> +					       0x00, 0x00, 0xc1);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x54, 0x94, 0x02, 0x85, 0x9f, 0x00,
> +					       0x6f, 0x00, 0x54, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11,
> +					       0x22, 0x20, 0x44, 0xff, 0x18, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x87, 0x47, 0x05, 0x05, 0x1c, 0x1c,
> +					       0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f,
> +					       0x0f, 0x0f, 0x0d, 0x0d, 0x13, 0x13, 0x11,
> +					       0x11, 0x24);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x06, 0x06, 0x04, 0x04, 0x1c, 0x1c,
> +					       0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f,
> +					       0x0e, 0x0e, 0x0c, 0x0c, 0x12, 0x12, 0x10,
> +					       0x10, 0x24);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x0e, 0x4b, 0x4b, 0x20, 0x19, 0x6b,
> +					       0x06, 0xb3);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2, 0xe3, 0x2b, 0x38, 0x08);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x00, 0x01, 0x00, 0x0e, 0x04, 0x44,
> +					       0x08, 0x10, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x80, 0x09, 0xff, 0xff, 0xff, 0xff,
> +					       0xff, 0xff);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x12, 0x03, 0x20, 0x00, 0xff);
> +	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00);
> +
> +	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
> +
> +	mipi_dsi_msleep(&dsi_ctx, 120);
> +
> +	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> +
> +	mipi_dsi_msleep(&dsi_ctx, 20);
> +
> +	return dsi_ctx.accum_err;
> +}
> +
>   static int boe_th101mb31ig002_disable(struct drm_panel *panel)
>   {
>   	struct boe_th101mb31ig002 *ctx = container_of(panel,
> @@ -115,12 +180,18 @@ static int boe_th101mb31ig002_disable(struct drm_panel *panel)
>   						      panel);
>   	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
>   
> +	if (ctx->desc->backlight_off_to_display_off_delay_ms)
> +		mipi_dsi_msleep(&dsi_ctx, ctx->desc->backlight_off_to_display_off_delay_ms);
> +
>   	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>   
>   	mipi_dsi_msleep(&dsi_ctx, 120);
>   
>   	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
>   
> +	if (ctx->desc->enter_sleep_to_reset_down_delay_ms)
> +		mipi_dsi_msleep(&dsi_ctx, ctx->desc->enter_sleep_to_reset_down_delay_ms);
> +
>   	return dsi_ctx.accum_err;
>   }
>   
> @@ -134,6 +205,9 @@ static int boe_th101mb31ig002_unprepare(struct drm_panel *panel)
>   	gpiod_set_value_cansleep(ctx->enable, 0);
>   	regulator_disable(ctx->power);
>   
> +	if(ctx->desc->power_off_delay_ms)
> +		msleep(ctx->desc->power_off_delay_ms);
> +
>   	return 0;
>   }
>   
> @@ -151,6 +225,18 @@ static int boe_th101mb31ig002_prepare(struct drm_panel *panel)
>   		return ret;
>   	}
>   
> +	if (ctx->desc->vcioo_to_lp11_delay_ms)
> +		msleep(ctx->desc->vcioo_to_lp11_delay_ms);
> +
> +	if (ctx->desc->lp11_before_reset) {
> +		ret = mipi_dsi_dcs_nop(ctx->dsi);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	if (ctx->desc->lp11_to_reset_delay_ms)
> +		msleep(ctx->desc->lp11_to_reset_delay_ms);
> +
>   	gpiod_set_value_cansleep(ctx->enable, 1);
>   	msleep(50);
>   	boe_th101mb31ig002_reset(ctx);
> @@ -187,6 +273,36 @@ static const struct panel_desc boe_th101mb31ig002_desc = {
>   	.init = boe_th101mb31ig002_enable,
>   };
>   
> +static const struct drm_display_mode starry_er88577_default_mode = {
> +	.clock	= (800 + 25 + 25 + 25) * (1280 + 20 + 4 + 12) * 60 / 1000,
> +	.hdisplay = 800,
> +	.hsync_start = 800 + 25,
> +	.hsync_end = 800 + 25 + 25,
> +	.htotal = 800 + 25 + 25 + 25,
> +	.vdisplay = 1280,
> +	.vsync_start = 1280 + 20,
> +	.vsync_end = 1280 + 20 + 4,
> +	.vtotal = 1280 + 20 + 4 + 12,
> +	.width_mm = 135,
> +	.height_mm = 216,
> +	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct panel_desc starry_er88577_desc = {
> +	.modes = &starry_er88577_default_mode,
> +	.lanes = 4,
> +	.format = MIPI_DSI_FMT_RGB888,
> +	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> +		      MIPI_DSI_MODE_LPM,
> +	.init = starry_er88577_init_cmd,
> +	.lp11_before_reset = true,
> +	.vcioo_to_lp11_delay_ms = 5,
> +	.lp11_to_reset_delay_ms = 50,
> +	.backlight_off_to_display_off_delay_ms = 100,
> +	.enter_sleep_to_reset_down_delay_ms = 100,
> +	.power_off_delay_ms = 1000,
> +};
> +
>   static int boe_th101mb31ig002_get_modes(struct drm_panel *panel,
>   					struct drm_connector *connector)
>   {
> @@ -312,6 +428,9 @@ static const struct of_device_id boe_th101mb31ig002_of_match[] = {
>   	{ .compatible = "boe,th101mb31ig002-28a",
>   	  .data = &boe_th101mb31ig002_desc
>   	},
> +	{ .compatible = "starry,er88577",
> +	  .data = &starry_er88577_desc
> +	},
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(of, boe_th101mb31ig002_of_match);

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>

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