| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <a64fdf95-9b9c-4ee5-878a-21a71a2dd5ad@linaro.org>
Date: Mon, 8 Jul 2024 14:39:40 +0200
From: neil.armstrong@...aro.org
To: Manikandan Muralidharan <manikandan.m@...rochip.com>, megi@....cz,
javierm@...hat.com, quic_jesszhan@...cinc.com, sam@...nborg.org,
airlied@...il.com, daniel@...ll.ch, maarten.lankhorst@...ux.intel.com,
mripard@...nel.org, tzimmermann@...e.de, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] drm/panel: himax-hx8394: Add Support for Microchip
AC40T08A MIPI Display Panel
On 01/07/2024 10:58, Manikandan Muralidharan wrote:
> Add support for the Microchip AC40T08A MIPI Display panel. This panel uses
> a Himax HX8394 display controller and requires a vendor provided init
> sequence. The display resolution is 720x1280@...z with width and height
> of 76mm and 132mm respectively.
>
> Signed-off-by: Manikandan Muralidharan <manikandan.m@...rochip.com>
> ---
> drivers/gpu/drm/panel/panel-himax-hx8394.c | 151 +++++++++++++++++++++
> 1 file changed, 151 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
> index d0e44f1f85d9..bf6bac5d5c12 100644
> --- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
> +++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
> @@ -339,6 +339,156 @@ static const struct hx8394_panel_desc powkiddy_x55_desc = {
> .init_sequence = powkiddy_x55_init_sequence,
> };
>
> +static int mchp_ac40t08a_init_sequence(struct hx8394 *ctx)
> +{
> + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> +
> + /* DCS commands do not seem to be sent correclty without this delay */
> + msleep(20);
> +
> + /* 5.19.8 SETEXTC: Set extension command (B9h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
> + 0xff, 0x83, 0x94);
> +
> + /* 5.19.9 SETMIPI: Set MIPI control (BAh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
> + 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
> +
> + /* 5.19.2 SETPOWER: Set power (B1h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
> + 0x48, 0x12, 0x72, 0x09, 0x32, 0x54,
> + 0x71, 0x71, 0x57, 0x47);
> +
> + /* 5.19.3 SETDISP: Set display related register (B2h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
> + 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);
> +
> + /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
> + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
> + 0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f,
> + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
> + 0x01, 0x0c, 0x86);
> +
> + /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
> + 0x6e, 0x6e);
> +
> + /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
> + 0x00, 0x00, 0x07, 0x07, 0x40, 0x07,
> + 0x0c, 0x00, 0x08, 0x10, 0x08, 0x00,
> + 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a,
> + 0x02, 0x15, 0x06, 0x05, 0x06, 0x47,
> + 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
> + 0x07, 0x0c, 0x40);
> +
> + /* 5.19.20 Set GIP Option1 (D5h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
> + 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01,
> + 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
> + 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25,
> + 0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> + 0x18, 0x18, 0x20, 0x21, 0x18, 0x18,
> + 0x18, 0x18);
> +
> + /* 5.19.21 Set GIP Option2 (D6h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
> + 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06,
> + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
> + 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20,
> + 0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> + 0x18, 0x18, 0x25, 0x24, 0x18, 0x18,
> + 0x18, 0x18);
> +
> + /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
> + 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21,
> + 0x24, 0x22, 0x47, 0x56, 0x65, 0x66,
> + 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d,
> + 0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61,
> + 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
> + 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24,
> + 0x22, 0x47, 0x56, 0x65, 0x65, 0x6e,
> + 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99,
> + 0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67,
> + 0x6b, 0x72, 0x7f, 0x7f);
> +
> + /* Unknown command, not listed in the HX8394-F datasheet (C0H) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
> + 0x1f, 0x73);
> +
> + /* Set CABC control (C9h)*/
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC,
> + 0x76, 0x00, 0x30);
> +
> + /* 5.19.17 SETPANEL (CCh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
> + 0x0b);
> +
> + /* Unknown command, not listed in the HX8394-F datasheet (D4h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
> + 0x02);
> +
> + /* 5.19.11 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
> + 0x02);
> +
> + /* 5.19.11 Set register bank (D8h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
> +
> + /* 5.19.11 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
> + 0x00);
> +
> + /* 5.19.11 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
> + 0x01);
> +
> + /* 5.19.2 SETPOWER: Set power (B1h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
> + 0x00);
> +
> + /* 5.19.11 Set register bank (BDh) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
> + 0x00);
> +
> + /* Unknown command, not listed in the HX8394-F datasheet (C6h) */
> + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
> + 0xed);
> +
> + return 0;
> +}
> +
> +static const struct drm_display_mode mchp_ac40t08a_mode = {
> + .hdisplay = 720,
> + .hsync_start = 720 + 12,
> + .hsync_end = 720 + 12 + 24,
> + .htotal = 720 + 12 + 12 + 24,
> + .vdisplay = 1280,
> + .vsync_start = 1280 + 13,
> + .vsync_end = 1280 + 14,
> + .vtotal = 1280 + 14 + 13,
> + .clock = 60226,
> + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> + .width_mm = 76,
> + .height_mm = 132,
> +};
> +
> +static const struct hx8394_panel_desc mchp_ac40t08a_desc = {
> + .mode = &mchp_ac40t08a_mode,
> + .lanes = 4,
> + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
> + .format = MIPI_DSI_FMT_RGB888,
> + .init_sequence = mchp_ac40t08a_init_sequence,
> +};
> +
> static int hx8394_enable(struct drm_panel *panel)
> {
> struct hx8394 *ctx = panel_to_hx8394(panel);
> @@ -556,6 +706,7 @@ static void hx8394_remove(struct mipi_dsi_device *dsi)
> static const struct of_device_id hx8394_of_match[] = {
> { .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
> { .compatible = "powkiddy,x55-panel", .data = &powkiddy_x55_desc },
> + { .compatible = "microchip,ac40t08a-mipi-panel", .data = &mchp_ac40t08a_desc },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, hx8394_of_match);
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
Powered by blists - more mailing lists