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Message-Id: <20240709-k1-01-basic-dt-v4-2-ae5bb5e56aaf@gentoo.org>
Date: Tue, 09 Jul 2024 03:18:45 +0000
From: Yixun Lan <dlan@...too.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Samuel Holland <samuel.holland@...ive.com>,
Anup Patel <anup@...infault.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Lubomir Rintel <lkundrak@...sk>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org,
Jesse Taube <jesse@...osinc.com>, Jisheng Zhang <jszhang@...nel.org>,
Inochi Amaoto <inochiama@...look.com>, Icenowy Zheng <uwu@...nowy.me>,
Meng Zhang <zhangmeng.kevin@...cemit.com>,
Meng Zhang <kevin.z.m@...mail.com>, Yangyu Chen <cyy@...self.name>,
Yixun Lan <dlan@...too.org>, Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v4 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
From: Yangyu Chen <cyy@...self.name>
The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.
Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@...self.name>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Yixun Lan <dlan@...too.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b5..5ad9cb4103356 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -46,6 +46,7 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
+ - spacemit,x60
- thead,c906
- thead,c910
- thead,c920
--
2.45.2
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