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Message-ID: <20240709221211.2130456-1-wsadowski@marvell.com>
Date: Tue, 9 Jul 2024 15:12:02 -0700
From: Witold Sadowski <wsadowski@...vell.com>
To: <linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<devicetree@...r.kernel.org>
CC: <broonie@...nel.org>, <robh@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<pthombar@...ence.com>, Witold Sadowski <wsadowski@...vell.com>
Subject: [PATCH v10 0/9] Marvell HW overlay support for Cadence xSPI
This patch series adds support for the second version of the Marvell
hardware overlay for the Cadence xSPI IP block. The overlay is a hardware
change made around the original xSPI block. It extends xSPI features with
clock configuration, interrupt masking, and full-duplex, variable-length SPI
operations.
These functionalities allow the xSPI block to operate not only with memory
devices but also with simple SPI devices and TPM devices.
Example ACPI entry:
Device (SPI0) {
Name (_HID, "PRP0001") // ACPI_DT_NAMESPACE_HID
Name (_UID, 0)
Name (_DDN, "SPI controller 0")
Name (_CCA, ONE)
Method (_STA) {Return (0xF)}
Name (_CRS, ResourceTemplate() {
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000000000, // MinAddress
0x804000001037, // MaxAddress
0, // AddressTranslation
0x1038) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804010000000, // MinAddress
0x804010000007, // MaxAddress
0, // AddressTranslation
0x8) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000002000, // MinAddress
0x804000004027, // MaxAddress
0, // AddressTranslation
0x2028) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000008000, // MinAddress
0x804000008237, // MaxAddress
0, // AddressTranslation
0x238) // AddressLength
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) { 0x7A }
})
Name (_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "marvell,cn10-xspi-nor"},
Package () { "reg", 0x8040},
}
})
} // SPI0
Changes:
v10:
Modify SDMA operation - Read as much data as possible using ioread64_rep, complete transfer with
memcpy. Ignore first step if buffer is not alligned
Clean unnecesary tennary operators
Add spi_transfer_delay_exec call
Rename "current_cycle_count" to "current_transfer_length"
v9:
Split into smaller patches:
- Marvell overlay splitted into: PHY, Clock, Interrupt and SDMA ops
- ACPI support splitted into resource mapping, CS parameter reading and tx/rx bus length
Add separate ops and a few function pointers to distinguish between Cadence and Marvell:
- SDMA read handler.
- IRQ enable/disable handler
- Separate mem_ops for Marvell xSPI
Cleanup xfer code from magic numbers
Add more descriptive commit msg for xfer block
Use bitrev8 instead of custom bit reversal
Rework Marvell SDMA read operations
Add example ACPI entry
v8:
Rename xferbase to xfer
Rework DLL reset, to return non inverted boolean value
Rework STIG and SDMA status check, to return non inverted boolean value
v7:
Rebase patches to latest sources, changes in "Allow to read basic xSPI configuration
from ACPI"
Removed bugfix, as it was integrated to next tree from v6
v6:
Fix item order in cdns,xspi.yaml
v5:
Rework cdns,xspi.yaml file
Reword commit messages
Move mamory mapping to ACPI patch
Use devm_platform_ioremap_resource instead of two step mapping
v4:
Rename new Marvell registers to keep naming conventions
Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor
Various fixed for cdns,xspi.yaml file:
- Remove unnecesary parameters
- Link register xferbase with marvell,cn10-xspi-nor
- Move default values to .c file from device-tree
Clock configuration optimization
ACPI fixes:
- Remove incorrect ACPI match table
Added .data field to device_id, fixes for matching in ACPI and dtb case
Minor style comment changes
v3:
Removed all kconfig changes
Added device-tree mrvl,xspi-nor tag
v2:
Support for second overlay iteration
v1:
-
v0:
Initial support for v1 overlay
Witold Sadowski (9):
spi: dt-bindings: cadence: Add Marvell overlay bindings documentation
for Cadence XSPI
spi: cadence: Add static PHY configuration in Marvell overlay
spi: cadence: Add clock configuration for Marvell xSPI overlay
spi: cadence: Add Marvell SDMA operations
spi: cadence: Add Marvell xSPI interrupt changes
spi: cadence: Add Marvell xfer operation support
spi: cadence: Change resource mapping
spi: cadence: Change cs property reading.
spi: cadence: Try to read spi-tx/rx-bus width property using ACPI
.../devicetree/bindings/spi/cdns,xspi.yaml | 32 +-
drivers/spi/spi-cadence-xspi.c | 682 +++++++++++++++++-
2 files changed, 694 insertions(+), 20 deletions(-)
--
2.43.0
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