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Message-ID: <20240709081614.19993-1-linux@fw-web.de>
Date: Tue, 9 Jul 2024 10:16:13 +0200
From: Frank Wunderlich <linux@...web.de>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Rafał Miłecki <rafal@...ecki.pl>
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
Daniel Golle <daniel@...rotopia.org>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH v1] arm64: dts: mediatek: mt7988: add labels for different nodes
From: Frank Wunderlich <frank-w@...lic-files.de>
Current devicetree-nodes missing a label which allows to add aproperties
or phandles to them, so add them.
Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
Fixes: 660c230bf302 ("arm64: dts: mediatek: mt7988: add I2C controllers")
Fixes: 09ff2216a035 ("arm64: dts: mediatek: mt7988: add PWM controller")
Fixes: 09346afaba0a ("arm64: dts: mediatek: mt7988: add XHCI controllers")
Fixes: b616b403cbff ("arm64: dts: mediatek: mt7988: add clock controllers")
Fixes: 6c1d134a103f ("arm64: dts: mediatek: Add initial MT7988A and BPI-R4")
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 32 +++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index aa728331e876..9ced005b1595 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -14,28 +14,28 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a73";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a73";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a73";
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a73";
reg = <0x3>;
device_type = "cpu";
@@ -43,7 +43,7 @@ cpu@3 {
};
};
- oscillator-40m {
+ system_clk: oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@@ -86,7 +86,7 @@ infracfg: clock-controller@...01000 {
#clock-cells = <1>;
};
- clock-controller@...1b000 {
+ topckgen: clock-controller@...1b000 {
compatible = "mediatek,mt7988-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
@@ -99,13 +99,13 @@ watchdog: watchdog@...1c000 {
#reset-cells = <1>;
};
- clock-controller@...1e000 {
+ apmixedsys: clock-controller@...1e000 {
compatible = "mediatek,mt7988-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
};
- pwm@...48000 {
+ pwm: pwm@...48000 {
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
@@ -124,7 +124,7 @@ pwm@...48000 {
status = "disabled";
};
- i2c@...03000 {
+ i2c0: i2c@...03000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
<0 0x10217080 0 0x80>;
@@ -137,7 +137,7 @@ i2c@...03000 {
status = "disabled";
};
- i2c@...04000 {
+ i2c1: i2c@...04000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10217100 0 0x80>;
@@ -150,7 +150,7 @@ i2c@...04000 {
status = "disabled";
};
- i2c@...05000 {
+ i2c2: i2c@...05000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10217180 0 0x80>;
@@ -163,7 +163,7 @@ i2c@...05000 {
status = "disabled";
};
- usb@...90000 {
+ ssusb0: usb@...90000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
<0 0x11193e00 0 0x0100>;
@@ -177,7 +177,7 @@ usb@...90000 {
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
- usb@...00000 {
+ ssusb1: usb@...00000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
@@ -191,21 +191,21 @@ usb@...00000 {
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
- clock-controller@...40000 {
+ xfi_pll: clock-controller@...40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
#clock-cells = <1>;
};
- clock-controller@...00000 {
+ ethsys: clock-controller@...00000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- clock-controller@...31000 {
+ ethwarp: clock-controller@...31000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
--
2.43.0
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