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Message-ID: <20240709090132.117077-9-quic_varada@quicinc.com>
Date: Tue, 9 Jul 2024 14:31:31 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<angelogioacchino.delregno@...labora.com>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <ilia.lin@...nel.org>, <rafael@...nel.org>,
<viresh.kumar@...aro.org>, <ulf.hansson@...aro.org>,
<quic_sibis@...cinc.com>, <quic_varada@...cinc.com>,
<quic_rjendra@...cinc.com>, <otto.pflueger@...cue.de>,
<luca@...tu.xyz>, <danila@...xyga.com>, <quic_ipkumar@...cinc.com>,
<stephan.gerhold@...nkonzept.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-pm@...r.kernel.org>
Subject: [PATCH v5 8/9] soc: qcom: cpr3: Add IPQ9574 definitions
From: Praveenkumar I <quic_ipkumar@...cinc.com>
* Add thread, scaling factor, CPR descriptor defines to enable
CPR on IPQ9574.
* Skip 'acc' usage since IPQ9574 does not have acc
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
---
v5: Move the 'acc_desc' usage check to first patch
v4: s/silver//, s/cprh/cpr4/
Skip 'acc' related code as IPQ9574 does not have acc
v3: Fix patch author
Included below information in cover letter
v2: Fix Signed-off-by order
Depends:
[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
[2] https://github.com/quic-varada/cpr/commits/konrad/
---
drivers/pmdomain/qcom/cpr3.c | 140 ++++++++++++++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
index 08a306d86403..1abdec8c137e 100644
--- a/drivers/pmdomain/qcom/cpr3.c
+++ b/drivers/pmdomain/qcom/cpr3.c
@@ -2056,6 +2056,142 @@ static const struct cpr_acc_desc msm8998_cpr_acc_desc = {
.cpr_desc = &msm8998_cpr_desc,
};
+static const int ipq9574_scaling_factor[][CPR3_RO_COUNT] = {
+ /* Fuse Corner 0 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 1 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 2 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+ /* Fuse Corner 3 */
+ {
+ 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+ 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+ },
+};
+
+static const struct cpr_thread_desc ipq9574_thread = {
+ .controller_id = 0,
+ .hw_tid = 0,
+ .ro_scaling_factor = ipq9574_scaling_factor,
+ .sensor_range_start = 0,
+ .sensor_range_end = 6,
+ .init_voltage_step = 10000,
+ .init_voltage_width = 6,
+ .step_quot_init_min = 0,
+ .step_quot_init_max = 15,
+ .num_fuse_corners = 4,
+ .fuse_corner_data = (struct fuse_corner_data[]){
+ /* fuse corner 0 */
+ {
+ .ref_uV = 725000,
+ .max_uV = 725000,
+ .min_uV = 725000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 4,
+ .max_quot_scale = 10,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 1 */
+ {
+ .ref_uV = 862500,
+ .max_uV = 862500,
+ .min_uV = 725000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 500,
+ .max_quot_scale = 800,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ /* fuse corner 2 */
+ {
+ .ref_uV = 987500,
+ .max_uV = 987500,
+ .min_uV = 787500,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 280,
+ .max_quot_scale = 650,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+
+ },
+ /* fuse corner 3 */
+ {
+ .ref_uV = 1062500,
+ .max_uV = 1062500,
+ .min_uV = 850000,
+ .range_uV = 0,
+ .volt_cloop_adjust = 0,
+ .volt_oloop_adjust = 0,
+ .max_volt_scale = 430,
+ .max_quot_scale = 800,
+ .quot_offset = 0,
+ .quot_scale = 1,
+ .quot_adjust = 0,
+ .quot_offset_scale = 5,
+ .quot_offset_adjust = 0,
+ },
+ },
+};
+
+static const struct cpr_desc ipq9574_cpr_desc = {
+ .cpr_type = CTRL_TYPE_CPR4,
+ .num_threads = 1,
+ .apm_threshold = 850000,
+ .apm_crossover = 880000,
+ .apm_hysteresis = 0,
+ .cpr_base_voltage = 700000,
+ .cpr_max_voltage = 1100000,
+ .timer_delay_us = 5000,
+ .timer_cons_up = 0,
+ .timer_cons_down = 0,
+ .up_threshold = 2,
+ .down_threshold = 2,
+ .idle_clocks = 15,
+ .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
+ .count_repeat = 1,
+ .gcnt_us = 1,
+ .vreg_step_fixed = 12500,
+ .vreg_step_up_limit = 1,
+ .vreg_step_down_limit = 1,
+ .vdd_settle_time_us = 34,
+ .corner_settle_time_us = 6,
+ .reduce_to_corner_uV = true,
+ .hw_closed_loop_en = false,
+ .threads = (const struct cpr_thread_desc *[]) {
+ &ipq9574_thread,
+ },
+};
+
+static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
+ .cpr_desc = &ipq9574_cpr_desc,
+};
+
static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
/* Same RO factors for all fuse corners */
{
@@ -2676,7 +2812,8 @@ static int cpr_probe(struct platform_device *pdev)
desc = data->cpr_desc;
/* CPRh disallows MEM-ACC access from the HLOS */
- if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH)
+ if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH &&
+ !of_device_is_compatible(dev->of_node, "qcom,ipq9574-cpr4"))
return -EINVAL;
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
@@ -2828,6 +2965,7 @@ static void cpr_remove(struct platform_device *pdev)
}
static const struct of_device_id cpr3_match_table[] = {
+ { .compatible = "qcom,ipq9574-cpr4", .data = &ipq9574_cpr_acc_desc },
{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
{ }
--
2.34.1
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