Message-ID: <20240709133610.1089420-1-stewart.hildebrand@amd.com>
Date: Tue, 9 Jul 2024 09:35:57 -0400
From: Stewart Hildebrand <stewart.hildebrand@....com>
To: Bjorn Helgaas <bhelgaas@...gle.com>, Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Dave Hansen
	<dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>
CC: Stewart Hildebrand <stewart.hildebrand@....com>, <x86@...nel.org>,
	<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 0/6] PCI: align small (<4k) BARs

This series sets the default minimum resource alignment to 4k for memory
BARs. In preparation, it makes an optimization and addresses some corner
cases observed when reallocating BARs. I consider the prepapatory
patches to be prerequisites to changing the default BAR size.

Issues observed when small (<4k) BARs are not 4k aligned are:

1. Devices to be passed through (to e.g. a Xen HVM guest) with small
(<4k) BARs require each memory BAR to be page aligned. Currently, the
only way to guarantee this alignment from a user perspective is to fake
the size of the BARs using the pci=resource_alignment= option. This is a
bad user experience, and faking the BAR size is not always desirable.
See the comment in drivers/pci/pci.c:pci_request_resource_alignment()
for further discussion.

Anecdotally, we're using pcitest for PCI passthrough validation with
Xen, and pcitest fails with a fake BAR size.

2. Devices with multiple small (<4k) BARs could have the MSI-X tables
located in one of its small (<4k) BARs. This may lead to the MSI-X
tables being mapped in the same 4k region as other data. The PCIe 6.1
specification (section 7.7.2 MSI-X Capability and Table Structure) says
we probably shouldn't do that.

To improve the user experience, and increase conformance to PCIe spec,
set the default minimum resource alignment of memory BARs to 4k. Choose
4k (rather than PAGE_SIZE) for the alignment value in the common code,
since that is the value called out in the PCIe 6.1 spec, section 7.7.2.
The new default alignment may be overridden by arches by implementing
pcibios_default_alignment(), or by the user with the
pci=resource_alignment= option.

I considered introducing checks for the specific scenarios described,
but chose not to pursue this. A check such as "if (xen_domain())" may be
pretty simple, but that doesn't account for other hypervisors. If other
hypervisors are to be considered, or if we try to dynamically reallocate
BARs for devices being marked for passthrough, such a check may quickly
grow unwieldy. Further, checking for the MSI-X tables residing in a
small (<4k) BAR is unlikely to be a one-liner. Making 4k alignment the
default seems more robust.

I considered alternatively adding new functionality to the
pci=resource_alignment= option, but that approach was already attempted
and decided against [1].

[1] https://lore.kernel.org/linux-pci/1473757234-5284-4-git-send-email-xyjxie@linux.vnet.ibm.com/

Comment from pci_request_resource_alignment() pasted here for reference:

    /*
     * Increase the alignment of the resource.  There are two ways we
     * can do this:
     *
     * 1) Increase the size of the resource.  BARs are aligned on their
     *    size, so when we reallocate space for this resource, we'll
     *    allocate it with the larger alignment.  This also prevents
     *    assignment of any other BARs inside the alignment region, so
     *    if we're requesting page alignment, this means no other BARs
     *    will share the page.
     *
     *    The disadvantage is that this makes the resource larger than
     *    the hardware BAR, which may break drivers that compute things
     *    based on the resource size, e.g., to find registers at a
     *    fixed offset before the end of the BAR.
     *
     * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
     *    set r->start to the desired alignment.  By itself this
     *    doesn't prevent other BARs being put inside the alignment
     *    region, but if we realign *every* resource of every device in
     *    the system, none of them will share an alignment region.
     *
     * When the user has requested alignment for only some devices via
     * the "pci=resource_alignment" argument, "resize" is true and we
     * use the first method.  Otherwise we assume we're aligning all
     * devices and we use the second.
     */

Stewart Hildebrand (6):
  PCI: don't clear already cleared bit
  PCI: restore resource alignment
  PCI: restore memory decoding after reallocation
  x86: PCI: preserve IORESOURCE_STARTALIGN alignment
  PCI: don't reassign resources that are already aligned
  PCI: align small (<4k) BARs

 arch/x86/pci/i386.c     |  7 +++++--
 drivers/pci/pci.c       | 17 +++++++++++++---
 drivers/pci/setup-bus.c | 44 +++++++++++++++++++++++++++++++++++++++++
 include/linux/pci.h     |  2 ++
 4 files changed, 65 insertions(+), 5 deletions(-)

-- 
2.45.2

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