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Message-Id: <20240710221630.29561-13-james.quinlan@broadcom.com>
Date: Wed, 10 Jul 2024 18:16:26 -0400
From: Jim Quinlan <james.quinlan@...adcom.com>
To: linux-pci@...r.kernel.org,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Cyril Brulebois <kibi@...ian.org>,
Stanimir Varbanov <svarbanov@...e.de>,
Krzysztof Kozlowski <krzk@...nel.org>,
bcm-kernel-feedback-list@...adcom.com,
jim2101024@...il.com,
james.quinlan@...adcom.com
Cc: Florian Fainelli <florian.fainelli@...adcom.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
linux-rpi-kernel@...ts.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@...ts.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v3 12/12] PCI: brcmstb: Enable 7712 SOCs
The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).
Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@...e.de>
---
drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index b6b21e0a56a8..3bc6b49227fe 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1192,6 +1192,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
+ /* 7712 does not have this (RGR1) timer */
+ if (pcie->model == BCM7712)
+ return;
+
/* Each unit in timeout register is 1/216,000,000 seconds */
writel(216 * timeout_us, pcie->base + REG_OFFSET);
}
@@ -1663,6 +1667,13 @@ static const int pcie_offsets_bmips_7425[] = {
[PCIE_INTR2_CPU_BASE] = 0x4300,
};
+static const int pcie_offset_bcm7712[] = {
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+ [PCIE_HARD_DEBUG] = 0x4304,
+ [PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
static const struct pcie_cfg_data generic_cfg = {
.offsets = pcie_offsets,
.model = GENERIC,
@@ -1728,6 +1739,14 @@ static const struct pcie_cfg_data bcm7216_cfg = {
.num_inbound = 3,
};
+static const struct pcie_cfg_data bcm7712_cfg = {
+ .offsets = pcie_offset_bcm7712,
+ .perst_set = brcm_pcie_perst_set_7278,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+ .model = BCM7712,
+ .num_inbound = 10,
+};
+
static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1737,6 +1756,7 @@ static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+ { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
{},
};
--
2.17.1
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