linux-kernel - Re: [PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

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Message-Id: <172061321610.624103.9680592794561118105.b4-ty@kernel.org>
Date: Wed, 10 Jul 2024 13:39:03 +0100
From: Will Deacon <will@...nel.org>
To: Joerg Roedel <joro@...tes.org>,
	Robin Murphy <robin.murphy@....com>,
	Kevin Tian <kevin.tian@...el.com>,
	Louis Maliyam <louispm@...gle.com>,
	Lu Baolu <baolu.lu@...ux.intel.com>
Cc: catalin.marinas@....com,
	kernel-team@...roid.com,
	Will Deacon <will@...nel.org>,
	iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

On Tue, 09 Jul 2024 23:26:41 +0800, Lu Baolu wrote:
> The aligned pages for cache invalidation returned by
> calculate_psi_aligned_address() are incorrect if the start pfn is not
> aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
> uses the number of pages to flush caches for the first-stage
> translation.
> 
> Fix this by updating the aligned pages once the address mask is adjusted.
> 
> [...]

Applied to iommu (intel/vt-d), thanks!

[1/2] iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
      https://git.kernel.org/iommu/c/c420a2b4e8be
[2/2] iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()
      https://git.kernel.org/iommu/c/0a3f6b346301

Cheers,
-- 
Will

https://fixes.arm64.dev
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