linux-kernel - Re: [PATCH v2 09/12] i2c: riic: Add support for fast mode plus

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Message-ID: <CAMuHMdWTYfK6aVi5BzBtQg_zQWjuZX7d7QHr3a4GAb+dQOWyvQ@mail.gmail.com>
Date: Thu, 11 Jul 2024 09:53:43 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: claudiu beznea <claudiu.beznea@...on.dev>
Cc: chris.brandt@...esas.com, andi.shyti@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, magnus.damm@...il.com, 
	mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de, 
	wsa+renesas@...g-engineering.com, linux-renesas-soc@...r.kernel.org, 
	linux-i2c@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v2 09/12] i2c: riic: Add support for fast mode plus

Hi Claudiu,

On Wed, Jul 10, 2024 at 4:20 PM claudiu beznea <claudiu.beznea@...on.dev> wrote:
> On 28.06.2024 12:22, Geert Uytterhoeven wrote:
> > On Tue, Jun 25, 2024 at 2:14 PM Claudiu <claudiu.beznea@...on.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >>
> >> Fast mode plus is available on most of the IP variants that RIIC driver
> >> is working with. The exception is (according to HW manuals of the SoCs
> >> where this IP is available) the Renesas RZ/A1H. For this, patch
> >> introduces the struct riic_of_data::fast_mode_plus.
> >>
> >> Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by
> >> instantiating the RIIC frequency to 1MHz and issuing i2c reads on the
> >> fast mode plus capable devices (and the i2c clock frequency was checked on
> >> RZ/G3S).
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/i2c/busses/i2c-riic.c
> >> +++ b/drivers/i2c/busses/i2c-riic.c
> >> @@ -407,6 +413,9 @@ static int riic_init_hw(struct riic_dev *riic)
> >>         riic_writeb(riic, 0, RIIC_ICSER);
> >>         riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
> >>
> >> +       if (info->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ)
> >> +               riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);
> >
> > Unless FM+ is specified, RIIC_ICFER is never written to.
> > Probably the register should always be initialized, also to make sure
> > the FMPE bit is cleared when it was set by the boot loader, but FM+
> > is not to be used.
>
> Instead of clearing only this bit, what do you think about using
> reset_control_reset() instead of reset_control_deassert() in riic_i2c_probe()?
>
> HW manuals for all the devices listed in
> Documentation/devicetree/bindings/i2c/renesas,riic.yaml specifies that
> ICFER_FMPE register is initialized with a default value by reset. All the
> other registers are initialized with default values at reset (according to
> HW manuals). I've checked it on RZ/G3S and it behaves like this.

RZ/A1 and RZ/A2M do not have reset controller support yet, so calling
reset_control_reset() is a no-op on these SoCs.

However, I overlooked that riic_init_hw() does an internal reset first
by setting the ICCR1_IICRST bit in RIIC_ICCR1.
Is that sufficient to reset the FMPE bit?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds