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Message-ID: <20240711090250.20827-1-johan+linaro@kernel.org>
Date: Thu, 11 Jul 2024 11:02:50 +0200
From: Johan Hovold <johan+linaro@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Abel Vesa <abel.vesa@...aro.org>,
linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Johan Hovold <johan+linaro@...nel.org>
Subject: [PATCH] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe
The DWC PCIe controller can be used with its internal MSI controller or
with an external one such as the GICv3 Interrupt Translation Service
(ITS).
Add the msi-map properties needed to use the GIC ITS. This will also
make Linux switch to the ITS implementation, which allows for assigning
affinity to individual MSIs.
Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 32a73ff672be..5822ed97ad87 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3114,6 +3114,8 @@ pcie6a: pci@...8000 {
linux,pci-domain = <7>;
num-lanes = <2>;
+ msi-map = <0x0 &gic_its 0xe0000 0x10000>;
+
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
@@ -3235,6 +3237,8 @@ pcie4: pci@...8000 {
linux,pci-domain = <5>;
num-lanes = <2>;
+ msi-map = <0x0 &gic_its 0xc0000 0x10000>;
+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
@@ -5394,8 +5398,6 @@ gic_its: msi-controller@...40000 {
msi-controller;
#msi-cells = <1>;
-
- status = "disabled";
};
};
--
2.44.2
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