linux-kernel - [PATCH 0/2] media: ov5675: Fixup ov5675 reset failures

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Message-Id: <20240711-linux-next-ov5675-v1-0-69e9b6c62c16@linaro.org>
Date: Thu, 11 Jul 2024 11:20:00 +0100
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: Sakari Ailus <sakari.ailus@...ux.intel.com>, 
 Mauro Carvalho Chehab <mchehab@...nel.org>, 
 Quentin Schulz <quentin.schulz@...obroma-systems.com>, 
 Jacopo Mondi <jacopo@...ndi.org>
Cc: Johan Hovold <johan@...nel.org>, 
 Kieran Bingham <kieran.bingham@...asonboard.com>, 
 linux-media@...r.kernel.org, linux-kernel@...r.kernel.org, 
 Bryan O'Donoghue <bryan.odonoghue@...aro.org>, stable@...r.kernel.org
Subject: [PATCH 0/2] media: ov5675: Fixup ov5675 reset failures

One long running saga for me on the Lenovo X13s is the occasional failure
to either probe or subsequently bring-up the ov5675 main RGB sensor on the
laptop.

Initially I suspected the PMIC for this part as the PMIC is using a new
interface on an I2C bus instead of an SPMI bus. In particular I thought
perhaps the I2C write to PMIC had completed but the regulator output hadn't
become stable from the perspective of the SoC. This however doesn't appear
to be the case - I can introduce a delay of milliseconds on the PMIC path
without resolving the sensor reset problem.

Secondly I thought about reset pin polarity or drive-strength but, again
playing about with both didn't yield decent results.

I also played with the duration of reset to no avail.

The error manifested as an I2C write timeout to the sensor which indicated
that the chip likely hadn't come out reset. An intermittent fault appearing
in perhaps 1/10 or 1/20 reset cycles.

Looking at the expression of the reset we see that there is a minimum time
expressed in XVCLK cycles between reset completion and first I2C
transaction to the sensor. The specification calls out the minimum delay @
8192 XVCLK cycles and the ov5675 driver meets that timing almost exactly.

A little too exactly - testing finally showed that we were too racy with
respect to the minimum quiescence between reset completion and first
command to the chip.

Fixing this error I choose to base the fix again on the number of clocks
but to also support any clock rate the chip could support by moving away
from a define to reading and using the XVCLK.

True enough only 19.2 MHz is currently supported but for the hypothetical
case where some other frequency is supported in the future, I wanted the
fix introduced in this series to still hold.

Hence this series:

1. Allows for any clock rate to be used in the valid range for the reset.
2. Elongates the post-reset period based on clock cycles which can now
vary.

Patch #2 can still be backported to stable irrespective of patch #1.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
---
Bryan O'Donoghue (2):
      media: ov5675: Derive delay cycles from the clock rate reported
      media: ov5675: Elongate reset to first transaction minimum gap

 drivers/media/i2c/ov5675.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)
---
base-commit: 523b23f0bee3014a7a752c9bb9f5c54f0eddae88
change-id: 20240710-linux-next-ov5675-60b0e83c73f1

Best regards,
-- 
Bryan O'Donoghue <bryan.odonoghue@...aro.org>