linux-kernel - Re: [PATCH v1 2/4] ata: ahci_imx: Clean up code by using i.MX8Q HSIO PHY driver

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Message-ID: <92bf088a-ffb4-4b15-ab00-5718d5b3c0ae@kernel.org>
Date: Thu, 11 Jul 2024 19:24:24 +0900
From: Damien Le Moal <dlemoal@...nel.org>
To: Richard Zhu <hongxing.zhu@....com>, tj@...nel.org, cassel@...nel.org,
 robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 shawnguo@...nel.org, s.hauer@...gutronix.de, festevam@...il.com
Cc: linux-ide@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 imx@...ts.linux.dev, kernel@...gutronix.de
Subject: Re: [PATCH v1 2/4] ata: ahci_imx: Clean up code by using i.MX8Q HSIO
 PHY driver

On 7/11/24 17:11, Richard Zhu wrote:
> Clean up code by using PHY interface.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---

[...]

>  static int imx8_sata_enable(struct ahci_host_priv *hpriv)
>  {
> -	u32 val, reg;
> -	int i, ret;
> +	u32 val;
> +	int ret;
>  	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
>  	struct device *dev = &imxpriv->ahci_pdev->dev;
>  
> -	/* configure the hsio for sata */
> -	ret = clk_prepare_enable(imxpriv->phy_pclk0);
> -	if (ret < 0) {
> -		dev_err(dev, "can't enable phy_pclk0.\n");
> +	/*
> +	 * Since "REXT" pin is only present for first lane of i.MX8QM
> +	 * PHY, it's calibration results will be stored, passed

s/it's/its

> +	 * through second lane PHY, and shared with all three lane PHYs.

s/through/through to the

> +	 *
> +	 * Initialize the first two lane PHYs here, although only the
> +	 * third lane PHY is used by SATA.
> +	 */

-- 
Damien Le Moal
Western Digital Research