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Message-Id: <a8741e38-837b-4fbb-8656-1e6d50bdfcc0@app.fastmail.com>
Date: Thu, 11 Jul 2024 09:53:30 +0800
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Maciej W. Rozycki" <macro@...am.me.uk>,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>
Cc: "Jonathan Corbet" <corbet@....net>, linux-doc@...r.kernel.org,
 linux-kernel@...r.kernel.org,
 "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 Philippe Mathieu-Daudé <philmd@...aro.org>
Subject: Re: [PATCH v3] MIPS: Implement ieee754 NAN2008 emulation mode



在2024年7月10日七月 下午5:21,Maciej W. Rozycki写道:
> On Wed, 10 Jul 2024, Thomas Bogendoerfer wrote:
>
>> > > I'm considering to apply your patch, how much testing/verification did
>> > > this patch see ? Do have some test binaries ?
>> > 
>> > It has been tested against Debian rootfs. There is no need to test againt special binary,
>> > but you need NaN2008 hardware such as Loongson 3A4000.
>> 
>> that's just one case, what about NaN2008 binaries on a legacy MIPS CPU ?
>
>  It would be good to check with hard-float QEMU configured for writable 
> FCSR.NAN2008 (which is one way original code was verified) that things 
> have not regressed.  And also what happens if once our emulation has 
> triggered for the unsupported FCSR.NAN2008 mode, an attempt is made to 
> flip the mode bit via ptrace(2), e.g. under GDB, which I reckon our 
> emulation permits for non-legacy CPUs (and which I think should not be 
> allowed under the new setting).

PTrace is working as expected (reflects emulated value).

The actual switchable NaN hardware (M5150, P5600) uses a dedicated Config7
bit rather than writable FCSR.NAN2008 to control NaN2008 mode. This is undocumented
and not present on some RTL releases. FCSR.NAN2008 is R/O as per The MIPS32 Instruction
Set Manual. This renders the purposed test pointless.

That being said, I'll catch some time later to test behaviour with purposed QEMU modification
but I think it's good to go now. 

Thanks
- Jiaxun

>
>   Maciej

-- 
- Jiaxun

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