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Message-Id: <20240711-macronix-mx25l3205d-fixups-v3-9-99353461dd2d@geanix.com>
Date: Thu, 11 Jul 2024 15:00:09 +0200
From: Esben Haabendal <esben@...nix.com>
To: Tudor Ambarus <tudor.ambarus@...aro.org>,
Pratyush Yadav <pratyush@...nel.org>, Michael Walle <mwalle@...nel.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Claudiu Beznea <claudiu.beznea@...on.dev>
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
Rasmus Villemoes <rasmus.villemoes@...vas.dk>,
linux-arm-kernel@...ts.infradead.org, Esben Haabendal <esben@...nix.com>
Subject: [PATCH v3 09/15] mtd: spi-nor: micron-st: Use new SPI_NOR_TRY_SFDP
flag
This converts from the old (deprecated) implicit way of triggering an
optional SFDP parse with fallback to the static configuration in the
matching struct flash_info entry.
Signed-off-by: Esben Haabendal <esben@...nix.com>
---
drivers/mtd/spi-nor/micron-st.c | 41 +++++++++++++++++++++--------------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c6499fdb712..c40e02b4f030 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -166,7 +166,8 @@ static const struct flash_info micron_nor_parts[] = {
.sector_size = SZ_128K,
.size = SZ_64M,
.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
- SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,
+ SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP |
+ SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
.fixups = &mt35xu512aba_fixups,
@@ -175,7 +176,7 @@ static const struct flash_info micron_nor_parts[] = {
.name = "mt35xu02g",
.sector_size = SZ_128K,
.size = SZ_256M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_4B_OPCODES,
},
@@ -364,38 +365,38 @@ static const struct flash_info st_nor_parts[] = {
.id = SNOR_ID(0x20, 0xba, 0x16),
.name = "n25q032",
.size = SZ_4M,
- .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
}, {
.id = SNOR_ID(0x20, 0xba, 0x17),
.name = "n25q064",
.size = SZ_8M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
}, {
.id = SNOR_ID(0x20, 0xba, 0x18),
.name = "n25q128a13",
.size = SZ_16M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00),
.name = "mt25ql256a",
.size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.fixup_flags = SPI_NOR_4B_OPCODES,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xba, 0x19),
.name = "n25q256a",
.size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00),
.name = "mt25ql512a",
.size = SZ_64M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.fixup_flags = SPI_NOR_4B_OPCODES,
.mfr_flags = USE_FSR,
}, {
@@ -404,7 +405,7 @@ static const struct flash_info st_nor_parts[] = {
.size = SZ_64M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xba, 0x21),
@@ -412,38 +413,38 @@ static const struct flash_info st_nor_parts[] = {
.size = SZ_128M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xba, 0x22),
.name = "mt25ql02g",
.size = SZ_256M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixups = &mt25q02_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x15),
.name = "n25q016a",
.size = SZ_2M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x16),
.name = "n25q032a",
.size = SZ_4M,
- .no_sfdp_flags = SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x17),
.name = "n25q064a",
.size = SZ_8M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x18),
.name = "n25q128a11",
.size = SZ_16M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00),
@@ -451,14 +452,14 @@ static const struct flash_info st_nor_parts[] = {
.size = SZ_32M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.fixup_flags = SPI_NOR_4B_OPCODES,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x19),
.name = "n25q256ax1",
.size = SZ_32M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
@@ -473,7 +474,7 @@ static const struct flash_info st_nor_parts[] = {
.size = SZ_64M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
@@ -484,14 +485,14 @@ static const struct flash_info st_nor_parts[] = {
.id = SNOR_ID(0x20, 0xbb, 0x21),
.name = "n25q00a",
.size = SZ_128M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x22),
.name = "mt25qu02g",
.size = SZ_256M,
- .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_TRY_SFDP,
.mfr_flags = USE_FSR,
.fixups = &mt25q02_fixups,
}
--
2.45.2
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