lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <29d388a8-b529-6af1-d3a3-a0846e1f0692@linux.intel.com>
Date: Thu, 11 Jul 2024 18:27:13 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: superm1@...nel.org
cc: Bjorn Helgaas <bhelgaas@...gle.com>, 
    Mathias Nyman <mathias.nyman@...el.com>, 
    Mika Westerberg <mika.westerberg@...ux.intel.com>, 
    "open list : PCI SUBSYSTEM" <linux-pci@...r.kernel.org>, 
    open list <linux-kernel@...r.kernel.org>, 
    "open list : USB XHCI DRIVER" <linux-usb@...r.kernel.org>, 
    Daniel Drake <drake@...lessos.org>, Gary Li <Gary.Li@....com>, 
    Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
    Mario Limonciello <mario.limonciello@....com>
Subject: Re: [PATCH v2 2/4] PCI: Verify functions currently in D3cold have
 entered D0

On Wed, 10 Jul 2024, superm1@...nel.org wrote:

> From: Mario Limonciello <mario.limonciello@....com>
> 
> It is reported that USB4 routers and downstream devices may behave
> incorrectly if a dock cable is plugged in at approximately the time that
> the autosuspend_delay is configured. In this situation the device has
> attempted to enter D3cold, but didn't finish D3cold entry when the PCI
> core tried to transition it back to D0.
> 
> Empirically measuring this situation an "aborted" D3cold exit takes
> ~60ms and a "normal" D3cold exit takes ~10ms.
> 
> The PCI-PM 1.2 spec specifies that the restore time for functions
> in D3cold is either 'Full context restore or boot latency'.
> 
> As PCIe r6.0 sec 5.8 specifies that the device will have gone
> through a conventional reset it may take some time for the

I'd add comma after reset.

The code change looks okay though,

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>

> device to be ready.
> 
> Wait up to 1 sec as specified in PCIe r6.0 sec 6.6.1 for a device
> in D3cold to return to D0.
> 
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  drivers/pci/pci.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 4ad02ad640518..9af324ab6bb02 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1388,6 +1388,17 @@ int pci_power_up(struct pci_dev *dev)
>  	else if (state == PCI_D2)
>  		udelay(PCI_PM_D2_DELAY);
>  
> +	/*
> +	 * D3cold -> D0 will have gone through a conventional reset and may need
> +	 * time to be ready.
> +	 */
> +	if (dev->current_state == PCI_D3cold) {
> +		int ret;
> +
> +		ret = pci_dev_wait(dev, "D3cold->D0", PCI_RESET_WAIT);
> +		if (ret)
> +			return ret;
> +	}
>  end:
>  	dev->current_state = PCI_D0;
>  	if (need_restore)
> 

-- 
 i.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ