linux-kernel - Re: [PATCH v3 1/3] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG

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Message-ID: <CA+V-a8t3GVMo8N=uBn58=S9=0MtuaCtxxN4OC5F-i7Vp8ntcpg@mail.gmail.com>
Date: Fri, 12 Jul 2024 14:47:27 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Magnus Damm <magnus.damm@...il.com>, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: clock: renesas: Document RZ/V2H(P)
 SoC CPG

Hi Geert,

Thank you for the review.

On Fri, Jul 12, 2024 at 12:58 PM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
>
<snip>
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> > +  '#clock-cells':
> > +    description: |
> > +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> > +        and a core clock reference, as defined in
> > +        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
> > +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> > +        a module number.  The module number is calculated as the CLKON register
> > +        offset index multiplied by 16, plus the actual bit in the register
> > +        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
> > +        calculation is (1 * 16 + 3) = 19.
>
> Using hexadecimal for the final number may be more readable,
> also in the DTS?
>
> (1 * 16 + 3) = 0x13?
>
Agreed I will update the value to hex.

> > +    const: 2
> > +
> > +  '#power-domain-cells':
> > +    const: 0
> > +
> > +  '#reset-cells':
> > +    description:
> > +      The single reset specifier cell must be the reset number. The reset number
> > +      is calculated as the reset register offset index multiplied by 16, plus the
> > +      actual bit in the register used to reset the specific IP block. For example,
> > +      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 48.
>
> (3 * 16 + 0) = 0x30?
>
OK.

> > --- /dev/null
> > +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
>
> __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
>
> [...]
>
> > +#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */
>
> __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
>
Oops, I missed updating it after the file name change.

Cheers,
Prabhakar