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Message-Id: <87209180-c09f-4536-b515-82e0ff260644@app.fastmail.com>
Date: Sun, 14 Jul 2024 11:02:55 +0800
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Huacai Chen" <chenhuacai@...nel.org>
Cc: "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>,
 "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] MIPS: Loongson64: Switch to SYNC_R4K



在2024年7月14日七月 上午11:00,Jiaxun Yang写道:
> 在2024年7月14日七月 上午10:54,Huacai Chen写道:
>> On Sun, Jul 14, 2024 at 10:41 AM Jiaxun Yang <jiaxun.yang@...goat.com> wrote:
>>>
>>> Nowadays SYNC_R4K is performing better than Loongson64's
>>> custom sync mechanism.
>> Loongson64's preciseness is significantly better than SYNC_R4K.
>
> My updated implementation[1] uses a multi-pass regression methodology
> which can compensite communication overhead. I had measured delta
> with EJTAG DINT on Loongson-2K and it can be reduced to as low as 4
> cycles while ASK_C0_COUNT has ~50 cycles delta.
>
> [1]: 
> https://lore.kernel.org/linux-mips/20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com/

This is currently in mips-next.

>
> Thanks
> - Jiaxun
>
>>
>> Huacai
>
>
> -- 
> - Jiaxun

-- 
- Jiaxun

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