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Message-ID: <202407160235.JYThNv91-lkp@intel.com>
Date: Tue, 16 Jul 2024 03:26:47 +0800
From: kernel test robot <lkp@...el.com>
To: Jonathan Neuschäfer <j.neuschaefer@....net>,
	openbmc@...ts.ozlabs.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org
Cc: oe-kbuild-all@...ts.linux.dev,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	linux-kernel@...r.kernel.org,
	Jonathan Neuschäfer <j.neuschaefer@....net>
Subject: Re: [PATCH RESEND v12 4/6] clk: wpcm450: Add Nuvoton WPCM450
 clock/reset controller driver

Hi Jonathan,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 4cece764965020c22cff7665b18a012006359095]

url:    https://github.com/intel-lab-lkp/linux/commits/Jonathan-Neusch-fer/dt-bindings-clock-Add-Nuvoton-WPCM450-clock-reset-controller/20240708-073926
base:   4cece764965020c22cff7665b18a012006359095
patch link:    https://lore.kernel.org/r/20240708-wpcm-clk-v12-4-1afac539c37d%40gmx.net
patch subject: [PATCH RESEND v12 4/6] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver
config: arm-randconfig-r064-20240715 (https://download.01.org/0day-ci/archive/20240716/202407160235.JYThNv91-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407160235.JYThNv91-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/clk/nuvoton/clk-wpcm450.c:55:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.

vim +55 drivers/clk/nuvoton/clk-wpcm450.c

    36	
    37	static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw,
    38							 unsigned long parent_rate)
    39	{
    40		struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw);
    41		unsigned long fbdv, indv, otdv;
    42		u64 rate;
    43		u32 pllcon;
    44	
    45		if (parent_rate == 0)
    46			return 0;
    47	
    48		pllcon = readl_relaxed(pll->pllcon);
    49	
    50		indv = FIELD_GET(PLLCON_INDV, pllcon) + 1;
    51		fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1;
    52		otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1;
    53	
    54		rate = (u64)parent_rate * fbdv;
  > 55		do_div(rate, indv * otdv);
    56	
    57		return rate;
    58	}
    59	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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