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Message-ID: <6daeb8fc-1f83-487f-a7c7-8c6769c6fc69@suse.de>
Date: Mon, 15 Jul 2024 13:36:24 +0300
From: Stanimir Varbanov <svarbanov@...e.de>
To: Jim Quinlan <james.quinlan@...adcom.com>, linux-pci@...r.kernel.org,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Cyril Brulebois <kibi@...ian.org>, Stanimir Varbanov <svarbanov@...e.de>,
Krzysztof Kozlowski <krzk@...nel.org>,
bcm-kernel-feedback-list@...adcom.com, jim2101024@...il.com
Cc: Florian Fainelli <florian.fainelli@...adcom.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@...ts.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG,
INTR2_CPU_BASE offsets SoC-specific
On 7/11/24 01:16, Jim Quinlan wrote:
> Our HW design has again changed a register offset which used to be standard
> for all Broadcom SOCs with PCIe cores. This difference is now reconciled
> for the registers HARD_DEBUG and INTR2_CPU_BASE.
>
> Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 39 ++++++++++++++++-----------
> 1 file changed, 24 insertions(+), 15 deletions(-)
>
Reviewed-by: Stanimir Varbanov <svarbanov@...e.de>
~Stan
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