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Message-ID: <20240715123301.1184833-1-s-vadapalli@ti.com>
Date: Mon, 15 Jul 2024 18:03:01 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
<s-vadapalli@...com>
Subject: [PATCH] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE output for PCIe1
The PCIe reference clock required by the PCIe Endpoints connected to the
PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM
is driven by the ACSPCIE module. Add the device-tree support for enabling
the same.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
---
Hello,
This patch is based on linux-next tagged next-20240715.
Patch **depends** on the series at:
https://lore.kernel.org/all/20240715120936.1150314-1-s-vadapalli@ti.com/
Patch has been tested on J784S4-EVM with the above series applied.
Logs:
https://gist.github.com/Siddharth-Vadapalli-at-TI/d825068cfe55bba7a869469c1ef64ddd
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index f170f80f00c1..62a6c7de3af6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
@@ -81,6 +82,11 @@ pcie3_ctrl: pcie3-ctrl@...c {
reg = <0x407c 0x4>;
};
+ acspcie0_proxy_ctrl: acspcie0-ctrl@...90 {
+ compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+ reg = <0x1a090 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@...0 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -1094,11 +1100,12 @@ pcie1_rc: pcie@...0000 {
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 333 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
--
2.40.1
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