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Message-ID: <CAP6Zq1jmhr4SHDG9+p=64T0AxgRTK7ufgDG7acrg=R5NnEp6JQ@mail.gmail.com>
Date: Tue, 16 Jul 2024 17:24:58 +0300
From: Tomer Maimon <tmaimon77@...il.com>
To: Jonas Gorski <jonas.gorski@...il.com>
Cc: linus.walleij@...aro.org, avifishman70@...il.com, tali.perry1@...il.com, 
	joel@....id.au, venture@...gle.com, yuenn@...gle.com, benjaminfair@...gle.com, 
	openbmc@...ts.ozlabs.org, linux-kernel@...r.kernel.org, 
	linux-gpio@...r.kernel.org
Subject: Re: [PATCH v1 0/7] pinctrl: npcm8xx: pin configuration changes

Hi Jonas,

Thanks for your comment, will be addressed in next version.

Thanks,

Tomer

On Sat, 13 Jul 2024 at 15:35, Jonas Gorski <jonas.gorski@...il.com> wrote:
>
> Hi,
>
> On Fri, 12 Jul 2024 at 02:48, Tomer Maimon <tmaimon77@...il.com> wrote:
> >
> > This patch set addresses various pin configuration changes for the
> > Nuvoton NPCM8XX BMC SoC. The patches aim to enhance functionality,
> > remove unused pins, and improve overall pin management.
> >
> > Tomer Maimon (7):
> >   pinctrl: nuvoton: npcm8xx: clear polarity before set both edge
> >   pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36
> >   pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group
> >   pinctrl: nuvoton: npcm8xx: remove unused smb4den pin, group, function
> >   pinctrl: nuvoton: npcm8xx: remove unused lpcclk pin, group, function
> >   pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration
> >   pinctrl: nuvoton: npcm8xx: modify pins flags
>
> You also need to update
> Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
> for any changes that affect the device tree bindings (e.g.
> adding/removing functions/groups).
>
> Best Regards,
> Jonas

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